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24637 Rev 3.02 - August 10, 2004
AMD-8131TM PCI-X Tunnel Data Sheet
AMD-8131TM HyperTransportTM PCI-X Tunnel Data Sheet
1 Overview
Cover page
The AMD-8131TM HyperTransportTM PCI-XTunnel (referred to as the IC in this document) is a HyperTransportTM technology (referred to as link in this document) tunnel developed by AMD that provides two PCI-X bridges. 1.1 * Device Features HyperTransport technology tunnel with side A and side B. * Side A is 16 bits (input and output); side B is 8 bits. * Either side may connect to the host or to a downstream HyperTransport technology compliant device. * Each side supports HyperTransport technology-defined reduced bit widths: 8-bit, 4-bit, and 2-bit. * Each side supports transfer rates of 1600, 1200, 800, and 400 mega-transfers per second. * Maximum bandwidth is 6.4 gigabytes per second across side A (half upstream and half downstream) and 3.2 gigabytes per second across side B. * Independent transfer rate and bit width selection for each side. * Link disconnect protocol supported. * Two PCI-X (rev. 1.0) bridges: bridge A and bridge B. * Each bridge supports a 64-bit data bus. * Each bridge supports operational modes of PCI-X and legacy PCI revision 2.2 protocol. * Bridges support 133, 100, and 66 MHz transfer rates in PCI-X mode. * Bridges support 66 and 33 MHz transfer rates in PCI mode. * Independent transfer rates and operational modes for each bridge. * Each bridge includes support for up to 5 PCI masters with clock, request, and grant signals. * Each bridge includes an IOAPIC with four redirection registers. Legacy interrupt controller and IOAPIC modes supported. * SHPC-compliant hot plug controller and support. 37.5 x 37.5 millimeter, 829-pin BGA package. 3.3 volt PCI-X signaling; 1.2 volt link signaling; 1.8 volt core.
* *
AMD-8131TM Device Host HyperTransport Link 16 bits upstream, 16 bits downstream slots
TM
Side A tunnel
Side B
HyperTransport Link 8 bits upstream, 8 bits downstream slots
Downstream Device
PCI-X Bridge A
PCI-X Bridge B
Figure 1: System block diagram.
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(c) 2004 Advanced Micro Devices, Inc. All rights reserved.The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Trademarks AMD, the AMD Arrow logo, and combinations thereof, and AMD-8131 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. PCI-X is a registered trademark of the PCI-Special Interest Group (PCI-SIG). Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Table of Contents
1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Device Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Tunnel Link Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 PCI-X Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Test and Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 Power Plane Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Reset And Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.1 Non-Hot Plug Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 Hot Plug Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 Systemboard Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.2 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.3 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Tunnel Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.1 Link PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 PCI-X Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.1 Tags, UnitIDs, SeqIDs And Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2 Interrupt Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2.1 Error NMI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3 Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3.1 Multi-slot Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3.2 Single-Slot Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.3.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.3.3.1 Serial Data From The Power Controllers To The IC . . . . . . . . . . . . . . . . . . . . . . . 28 4.5.3.3.2 Serial Data From The IC To The Power Controllers . . . . . . . . . . . . . . . . . . . . . . . 29 4.5.3.4 SHPC Interrupts, Events, And Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.3.5 Reset To Hot Plug Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.4 PCI-X PHY Compensation Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.5 Transactions Claimed By The Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5.6 Various Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5.7 Error Conditions And Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6 Performance-Related Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1 Bandwidth Percentage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.2 Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Configuration Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Register Naming and Description Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40
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5.2 5.3 5.4 5.5 6
PCI-X Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI-X IOAPIC Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOAPIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHPC Working Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41 63 65 67 74 74 74 75 76
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 8 9
Ball Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.1 High Impedance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2 NAND Tree Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: System block diagram................................................................................................................... 1 Systemboard clocking. ................................................................................................................ 17 Correction for characterization. .................................................................................................. 18 System diagram for multiple hot plug slots on a bridge. ............................................................ 22 System diagram of PME# signals. .............................................................................................. 23 System diagram of M66EN signals. ........................................................................................... 23 Multi-slot hot plug enable/disable sequence............................................................................... 24 Single-slot hot plug system diagram........................................................................................... 25 Single-slot hot plug enable/disable sequence.............................................................................. 26 Single-slot hot plug M66EN connections. .................................................................................. 26 Hot plug serial interface connections.......................................................................................... 27 Configuration space. ................................................................................................................... 40 Ball designations. ........................................................................................................................ 77 Package mechanical drawing. ..................................................................................................... 82 NAND tree. ................................................................................................................................. 83
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List of Tables
Table 1: Table 2. Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: IO signal types. ............................................................................................................................. 7 Signal isolation groups................................................................................................................ 22 Channel 00b, interrupt capable serial hot plug data to the IC..................................................... 28 Channel 01b, non-interrupt capable serial hot plug data to the IC. ............................................ 29 Serial hot plug data from the IC to the power controller. ........................................................... 29 Bandwidth percentages. .............................................................................................................. 38 Some latencies............................................................................................................................. 39 Configuration spaces................................................................................................................... 41 Memory mapped address spaces................................................................................................. 41 Register attributes. ...................................................................................................................... 41 Absolute maximum ratings. ........................................................................................................ 74 Operating ranges. ........................................................................................................................ 74 Current and power consumption. ................................................................................................ 75 DC characteristics for signals on the VDD33 power plane. ....................................................... 75 AC requirements for REFCLK. .................................................................................................. 76 AC data for PCI clocks. .............................................................................................................. 76 AC data for PCI bus. ................................................................................................................... 76 Alphabetical listing of signals A_ACK64# to B_PRESET#. ..................................................... 78 Alphabetical listing of signals B_REQ0# to VDD18. ................................................................ 79 Alphabetical listing of signals VDD18 to VSS........................................................................... 80 Test modes................................................................................................................................... 83
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2
Ordering Information
AMD-8131
BL
C
Case Temperature C = Commercial temperature range Package Type BL = Organic Ball Grid Array with lid Family/Core AMD-8131TM device
3 3.1
Signal Descriptions Terminology
See section 5.1.2 for a description of the register naming convention used in this document. See the AMD-8131TM HyperTransportTM PCI-X Tunnel Design Guide for additional information. Signals with a # suffix are active low. Signals described in this chapter utilize the following IO cell types:
Name Input Output OD IO IOD Analog w/PU Notes Input signal only. Output signal only. This includes outputs that are capable of being in the high-impedance state. Open drain output. These signals are driven low and expected to be pulled high by external circuitry. Input or output signal. Input or open-drain output. Analog signal. With pullup. The signal includes a pullup resistor to the signal's power plane. The resistor value is nominally 8K ohms.
Table 1: IO signal types.
The following provides definitions and reference data about each of the IC pins. "During Reset" provides the state of the pin while RESET# is asserted. "After Reset" provides the state of the pin immediately after RESET# is deasserted. "Func." means that the pin is functional and operating per its defined function.
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3.2
Tunnel Link Signals
The following are signals associated with the HyperTransport links. [B, A] in the signal names below refer to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs.
Pin name and description LDTCOMP[3:0]. Link compensation pins for both sides of the tunnel. These are designed to be connected through resistors as follows: Bit [0] [1] [3, 2] Function Positive receive compensation Negative receive compensation Transmit compensation External Connection Resistor to VDD12B Resistor to VSS Resistor from bit [2] to bit [3] IO cell Power During After type plane* reset reset Analog VDD12A
These resistors are used by the compensation circuit. The output of this circuit is combined with DevA:0x[E8, E4, E0] to determine compensation values that are passed to the link PHYs. LRACAD_[P, N][15:0]; LRBCAD_[P, N][7:0]. Receive link command-addressdata bus. LRACLK[1, 0]_[P, N]; LRBCLK0_[P, N]. Receive link clock. LR[B, A]CTL_[P, N]. Receive link control signal. LTACAD_[P, N][15:0]; LTBCAD_[P, N][7:0]. Transmit link command-addressdata bus. LTACLK[1, 0]_[P, N]; LTBCLK0_[P, N]. Transmit link clock. LT[B, A]CTL_[P, N]. Transmit link control signal. Link VDD12 input Link VDD12 input Link VDD12 input Link VDD12 Diff Func. output High** Link VDD12 Func. output Link VDD12 Diff output Low** Func. Func.
* The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the B side of the tunnel are powered by VDD12B. ** Diff High and Diff Low for these link pins specify differential high and low; e.g., Diff High specifies that the _P signal is high and the _N signal is low. If one of the sides of the tunnel is not used on a platform, then the unconnected link should be treated as follows, for every 10 differential pairs: connect all of the _P differential inputs together and through a resistor to VSS; connect all the _N differential inputs together and through a resistor to VDD12; leave the differential outputs unconnected. If there are unused link signals on an active link (because the IC is connected to a device with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way.
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AMD-8131TM PCI-X Tunnel Data Sheet
3.3
[B, A] in the following signal names is used to differentiate between PCI-X bridge A and PCI-X bridge B. "Normal" refers to non-hot plug mode (DevA:0x48[HPENB, HPENA]) or hot plug mode with external isolation switches (Dev[B, A]:0x40[HPSSS#]); "Single slot HP" refers to hot plug mode while Dev[B, A]:0x40[HPSSS#] is low. When in "normal" mode, PCI-X signals that typically connect to the slot are placed into the "During reset" state when [B, A]_PRESET# is asserted; the other signals are placed into the "During reset" state only when RESET# is asserted. The "Single slot HP", "During reset" column refers to while RESET# is asserted for all the signals.
Pin name and description IO cell Power Normal Single slot HP type plane During After During After reset reset reset reset IO IO IO VDD33 3-State 3-State VDD33 VDD33 Low Low Parked Parked Low Low Low Low Low Low
[B, A]_ACK64#. PCI-X acknowledge for 64-bit transfers. [B, A]_AD[63:0]. PCI-X address-data bus. [B, A]_CBE_L[7:0]. PCI-X command-byte enable bus. A_COMPAT. Strapping option to specify if PCI-X bridge A is the default bus in the system. This may only be associated with PCI-X bridge A. See also DevA:0x48[COMPAT]. [B, A]_DEVSEL#. PCI-X device select signal. During reset, these signals may be 3-state or they may be driven, based on the requirements of the PCI-X initialization pattern. [B, A]_FRAME#. PCI-X frame signal.
Input VDD33
IO
VDD33 See left 3-State
Low
Low
IO
VDD33 3-State 3-State High High
Low [0] is Low; [4:1] are high
Low [0] is Low; [4:1] are high
[B, A]_GNT[4:0]#. PCI-X master grant signals. Some of these IO (See VDD33 left) signals are an input while PWROK is deasserted; all other times, they are outputs. [B, A]_GNT[4:3]# each require a strapping resistor to help specify the bridge operationg frequency after a PWROK reset; see section 4.2. Note: A_GNT[2:1] require weak pull-up resistors to VDD33. B_GNT2# is an input while PWROK is low and an output at all other times. As an input, it is used to specify the default state of DevB:0x40[HPSSS#]. HPSSS# specifies if the IC supports a single hot plug slot on the bridge without external isolation switches. A weak resistor should be tied from this signal to VDD33 or to ground. [B, A]_HPSORLC. Hot plug serial output reset latch clock output (alternate functions to [B, A]_GNT4# selected by hot plug mode, DevA:0x48[HPENA, HPENB]). These are used in support of the hot plug serial interface. See section 4.5.3.3 for details. [B, A]_IRDY#. PCI-X master ready signal. IO
VDD33 3-State 3-State
Low
Low
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Pin name and description
IO cell Power Normal Single slot HP type plane During After During After reset reset reset reset IOD VDD33 3-State 3-State Low Low
[B, A]_M66EN. Frequency select input for [B, A]_PCLK while in conventional PCI mode. When not in hot plug mode, the state of this signal is captured at the rising edge [B, A]_PRESET# and (see section 4.2.1). After the corresponding [B, A]_PRESET# signal goes high, the state of [B, A]_M66EN is ignored. In hot plug mode, this signal may be driven low as an output after initialization. [B, A]_PAR. PCI-X parity signal. [B, A]_PAR64. PCI-X upper 32-bit parity signal for 64-bit transfers. [B, A]_PCIXCAP. PCI-X frequency capabilities selection. The state of this signal is captured at the rising edge [B, A]_PRESET# and used to determine the bus mode (see section 4.2.1). After the corresponding [B, A]_PRESET# signal goes high, the state of [B, A]_PCIXCAP is ignored. [B, A]_PCLK[4:0]. Up to 133 MHz PCI-X clock outputs. [B, A]_HPSID. Hot plug serial input data (alternative function to [B, A]_PCLK4# selected by hot plug mode, DevA:0x48[HPENA, HPENB]). See section 4.5.3.3 for details. [B, A]_PERR#. PCI-X parity error. This signal is only applicable to parity errors on the secondary PCI-X bus interface. [B, A]_PIRQ[A, B, C, D]#. PCI-X interrupt requests. [B, A]_PIRQA# may be an input or an open-drain output in support of the hot plug controller. [B, A]_PIRQ[B, C, D]# are inputs only. [B, A]_PLLCLKI. PLL clock input. See section 4.3 for details. [B, A]_PME#. Power management event interrupt. The IC asserts this signal when SHPC-defined power management events occur. This signal is typically connected to the system Southbridge, where it may be used to initate system state transitions. [B, A]_PRESET#. Secondary PCI bus reset. This is asserted whenever RESET# is asserted or when programmed by Dev[B, A]:0x3C[SBRST]. Assertion of this pin does not reset any logic internal to the IC. Note: the PCI requirement for a delay between the rising edge of RST# and the first configuration access is not enforced by the IC with hardware; it is expected that this requirement be enforced through software. In hot plug mode, this is connected to [B, A]_HPSORR# of the power controller. See section 4.5.3.3 for details.
IO IO
VDD33 VDD33
Low Low
Func. Func.
Low Low
Low Low
Input VDD33
IO (See VDD33 Func. left)
Func.
[4:1]: Func. [0]: Low
[4:1]: Func. [0]: Low Low
IO
VDD33 3-State 3-State
Low
IOD; VDD33 3-State 3-State input Func.
Low
Low
[B, A]_PLLCLKO. PLL clock output. See section 4.3 for details. Output VDD33 Func. Input VDD33 OD
Func.
Func.
VDD33 3-State 3-State 3-State 3-State
Output VDD33
Low
High
Low
High
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AMD-8131TM PCI-X Tunnel Data Sheet
Pin name and description
IO cell Power Normal Single slot HP type plane During After During After reset reset reset reset [0]: [0]: IO (See VDD33 REQs REQs Low; Low; are left) are inputs; inputs; [3:1]: [3:1]: HP- inputs; inputs; HPHPSOLC: SOLC: HPHigh SOLC: SOLC: High High High IO VDD33 Low 3-State Low Low
[B, A]_REQ[4:0]#. PCI-X master request input signals. A_REQ[2:0]# are used for test-mode selection; see section 9. [B, A]_HPSOLC. Hot plug serial output latch clock (alternative function to [B, A]_REQ4 selected by hot plug mode, DevA:0x48[HPENA, HPENB]). See section 4.5.3.3 for details. [B, A]_REQ64#. PCI-X request for 64-bit transfers. The IC drives this signal to the asserted state while [B, A]_PRESET# is asserted. [B, A]_SERR#. PCI-X system error signal. [B, A]_STOP#. PCI-X target abort signal. During reset, these signals may be 3-state or they may be driven, based on the requirements of the PCI-X initialization pattern. [B, A]_TRDY#. PCI-X target ready signal. During reset, these signals may be 3-state or they may be driven, based on the requirements of the PCI-X initialization pattern.
Input VDD33 IO VDD33 See left 3-State
Low Low
Low Low
IO
VDD33 See left 3-State
Low
Low
HPSIC. Hot plug serial input clock; see section 4.5.3.3 for details. IO (See VDD33 This signal is an input only while PWROK is low and an output at left) all other times. As an input, it is used to specify the default state of DevA:0x40[HPSSS#]. HPSSS# specifies if the IC supports a single hot plug slot on the bridge without external isolation switches. A weak resistor should be tied from this signal to VDD33 or to ground. HPSIL#. Hot plug serial input load; see section 4.5.3.3 for details. IO (See VDD33 left) This signal is an input while PWROK is low and an output at all other times. As an input, it is used to specify if bridge B of the IC is in hot plug mode or not; the latched state is available in DevA:0x48[HPENB]. To specify that bridge B is in hot plug mode, a weak resistor to VDD33 should be placed on this signal. To specify that bridge B is not in hot plug mode, a weak pulldown resistor to ground should be placed on this node. When neither bridge A nor B are in hot plug mode, this signal is always driven high. HPSOC. Hot plug serial output clock; see section 4.5.3.3 for details. Output VDD33
High
High
High
High
High
High
High
High
High
High
High
High
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Pin name and description
IO cell Power Normal Single slot HP type plane During After During After reset reset reset reset Low High Low High
IO (See VDD33 HPSOD. Hot plug serial output data; see section 4.5.3.3 for details. This signal is an input while PWROK is low and an output left) at all other times. As an input, it is used to specify if bridge A of the IC is in hot plug mode or not; the latched state is available in DevA:0x48[HPENA]. To specify that bridge A is in hot plug mode, a weak resistor to VDD33 should be placed on this signal. To specify that bridge A is not in hot plug mode, a weak pulldown resistor to ground should be placed on this node. When neither bridge A nor B are in hot plug mode, this signal is always driven low. NIOAIRQ[A, B, C, D]#. Non-IOAPIC interrupt requests. Each of these signals require a weak pullup resistor to VDD33. In particular, if the state of NIOAIRQC# is low during the rising edge of PWROK, then the IC will enter a production test mode that results in undefined behavior in [B, A]_PLLCLKO and [B, A]_PLLCLKI. See section 4.5.2 and Dev[B, A]:0x40[NIOAMODE] for details about the function of these pins. P_CAL, P_CAL#. PCI-X PHY calibration pins. These are designed for the following external circuit: P_CAL should be connected through a resistor to ground; P_CAL# should be conneced through a resistor to VDD33. The calculated calibration values associated with these resistors are provided DevA:0x[54, 50][CALCCOMP]. OD
VDD33 3-State 3-State 3-State 3-State
Input VDD33
If a bridge is to be left unused, the signals associated with that bridge should be connected as follows: * The following signals do not require any connection: [B, A]_AD[63:0], [B, A]_CBE_L[7:0], [B, A]_PAR, [B, A]_PAR64, [B, A]_PCLK[4:0], [B, A]_PRESET#. * The following signals should be tied high through resistors: [B, A]_ACK64#, [B, A]_DEVSEL#, [B, A]_FRAME#, [B, A]_IRDY#, [B, A]_PERR#, [B, A]_PIRQ[D:A]#, [B, A]_REQ[4:0]#, [B, A]_SERR#, [B, A]_STOP#, [B, A]_TRDY#, [B, A]_GNT[4:0]#, [B, A]_PME#, [B, A]_REQ64#. * The following signals should be grounded: [B, A]_PCIXCAP, [B, A]_M66EN. * [B, A]_PLLCLKO should be connected to [B, A]_PLLCLKI. 3.4 Test and Miscellaneous Signals
IO cell Power During After type plane reset reset Input VDD33
Pin name and description CMPOVR. Link automatic compensation override. 0=Link automatic compensation is enabled. 1=The compensation values stored in DevA:0x[E0, E4, E8] control the compensation circuit. The state of this signal determines the default value for DevA:0x[E0, E4, E8][ACTL and BCTL] at the rising edge of PWROK. FREE[22:1]. These pins should be left unconnected. LDTSTOP#. Link disconnect control signal. This pin is also used for test-mode selection; see section 9. NC[3:0]. These pins should be left unconnected.
Input VDD33
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PWROK. Power OK. 1=All power planes are valid. The rising edge of this signal is deglitched; it is not observed internally until it is high for more than 6 consecutive REFCLK cycles. See section 4.2 for more details about this signal. REFCLK. 66 MHz reference clock. This is required to be operational and valid for a minimum of 200 microseconds prior to the rising edge of PWROK and always while PWROK is high. RESET#. Reset input. See section 4.2 for details. Note: RESET# is also used as the hot plug [B, A]_HPSOR# reset. When RESET# is asserted, the hot plug shift register and control latches are reset. RSVD[22:0]. These pins should be left unconnected. STRAPL[3:2]. Strapping options to be tied low. These pins should be tied to ground. TEST. This pin is required to be tied low for functional operation. See section 9 for details.
Input VDD33
Input VDD33
Input VDD33
Input VDD33 Input VDD33
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3.5
Power and Ground
VDD12[B, A]. 1.2 volt power plane for the HyperTransport technology pins. VDD12A provides power to the A side of the tunnel. VDD12B provides power to the B side of the tunnel. VDD18. 1.8-volt power plane for the core of the IC. VDDA18. Analog 1.8-volt power plane for the PLLs in the core of the IC. This power plane is required to be filtered from digital noise. VDD33. 3.3-volt power plane for IO. VSS. Ground. 3.5.1 Power Plane Sequencing
The following are power plane requirements that may imply power supply sequencing requirements. * VDD33 is required to always be higher than VDD18, VDDA18, and VDD12[B, A]. * VDD18 and VDDA18 are required to always be higher than VDD12[B, A]. 4 4.1 Functional Operation Overview
The IC connects to the host through either the side A or side B HyperTransportTM link interface. The other side of the tunnel may or may not be connected to another device. Host-initiated transactions that do not target the IC or the bridge flow through the tunnel to the downstream device. Transactions claimed by the device are passed to internal registers or to one of the PCI-X bridges. See section 5.1 for details about the software view of the IC. See section 5.1.2 for a description of the register naming convention. See the AMD-8131TM HyperTransportTM PCI-X Tunnel Design Guide for additional information. 4.2 Reset And Initialization
RESET# and PWROK are both required to be low while the power planes to the IC are invalid and for at least 1 millisecond after the power planes are valid. Deassertion of PWROK is referred to as a cold reset. After PWROK is brought high, RESET# is required to stay low for at least 1 additional millisecond. After RESET# is brought high, the links go through the initialization sequence. After a cold reset, the IC can be reset by asserting RESET# while PWROK remains high. This is referred to as a warm reset. RESET# must be asserted for no less than 1 millisecond during a warm reset.
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4.2.1
Non-Hot Plug Initialization
The operational mode (conventional PCI or PCI-X) and frequency of the PCI-X bridges ([B, A]_PCLK[4:0]) are determined after a cold reset by the [B, A]_PCIXCAP signals, the [B, A]_M66EN signals, and by strapping resistors on [B, A]_GNT[4:3] (the A_ signals specify bridge A and the B_ signals specify bridge B). For [B, A]_GNT[4:3], to select a 1, a pullup resistor to VDD33 is placed on the signal; to select a 0, a pulldown resistor to ground is placed on the signal. The mode and frequency is determined while PWROK is low and held after PWROK goes high. The options and associated selects are: GNT[4:3]# XXb XXb XXb 01b 00b PCIXCAP Grounded Grounded Middle voltage Pullup to VDD33 Pullup to VDD33 M66EN 0 1 X X X Mode Conventional PCI Conventional PCI PCI-X PCI-X PCI-X
Frequency 33.33 MHz 66.67 MHz 66.67 MHz 100.00 MHz 133.33 MHz
Supported R/G/P [4:0] [3:0] [3:0] [3:0] [2:0]
Notes to the above table: * X means that the state does not matter to the IC. * The GNT[4:3]# column shows the value latched by the IC while PWROK is low. * The PCIXCAP column indicates how the IC observes PCIXCAP. Grounded indicates PCIXCAP is tied to ground. Middle voltage indicates PCIXCAP is tied to a pullup resistor to VDD33 and between 1 and 5 parallel pulldown resisters to ground; these pulldown resistors may come from the systemboard and from cards located in up to four slots. Pullup to VDD33 indicates PCIXCAP is tied to a pullup resistor to VDD33 and no pulldown resistors. * The Supported R/G/P column indicates the sets of REQ#, GNT#, and PCLK signals that are supported by the IC's bridge in that mode (there may be other constraints such as electrical requirements that further limit the number of external devices supported). * If a bridge from the IC supports 5 slots, then only 33 MHz conventional PCI mode is supported. In this situation, M66EN and PCIXCAP should be grounded on the systemboard to the slots so that all PCI cards properly initialize. * The state of the straps is reflected in Dev[B, A]:0xA0[SCF] and Dev[B, A]:0x40[CPCI66] after a cold reset. * If the systemboard supports PCI-X mode operation for a bridge, then a pullup resistor to VDD33 must be placed on the bridge's PCIXCAP pin. To limit the frequency of a PCI-X-capable bridge to 66 MHz on a systemboard, the systemboard must also include a pulldown resistor from the bridge's PCIXCAP pin to ground. The strapping options on GNT[4:3]# are used to distinguish between systems that support 100MHz and 133 MHz; in either of these two cases, the system board should include no pulldown resistors on PCIXCAP. 4.2.2 Hot Plug Initialization
Bridges in hot plug mode are always placed into 33 MHz, conventional PCI mode after RESET# is asserted. The operational speed and mode are then initialized by software through the following steps: (1) initialization of write once registers in the SHPC[B, A]:XX register block, (2) optional execution of Power Only All Slots SHPC command, (3) acquisition of the capabilities and presence information for each slot by observing the RST#, M66EN, PCIXCAP, PRSNT1#, and PRSNT2# signals, (4) determination of the highest common bus frequency and mode that may be selected, (5) execution of Set Bus Segment Speed/Mode SHPC command for the selected speed and mode, and (6) execution of Enable All Slots SHPC command. This sequence is the same when hot plug single-slot support is selected (Dev[B, A]:0x40[HPSSS#]). However,
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all of the slot signals are forced low until the slot is powered. 4.3 Clocking It is required that REFCLK be valid in order for the IC to operate. Also, the LR[B, A]CLK inputs from the operation links must also be valid at the frequency defined DevA:0xCC[FREQA] and DevA:0xD0[FREQB]. The IC provides [B, A]_PCLK[4:0] as the clocks to the secondary bus devices. 4.3.1 Systemboard Requirements
The IC provides the PCI clocks for secondary-bus devices, [B, A]_PCLK[4:0], and a PLL feedback for itself, [B, A]_PLLCLKO to [B, A]_PLLCLKI. [B, A]_PLLCLKO is fixed at 66 MHz while [B, A]_PCLK[4:0] varies based on the specified secondary-bus frequency. The systemboard is required to include a loopback connection from [B, A]_PLLCLKO to [B, A]_PLLCLKI. The length of this connection is required to be approximately the same as the length of the [B, A]_PCLK traces from the IC to the external PCI devices (the length of the connection from A_PLLCLKO to A_PLLCLKI should be the same as the length of the A_PCLK signals and the length of the connection from B_PLLCLKO to B_PLLCLKI should be the same as the length of the B_PCLK signals) such that the flight time of the [B, A]_PCLK signals is the same as the flight time of the PLL feedback. Flight time is defined as the time difference between the rising edge of the clock as observed at the source of the systemboard trace ([B, A]_PLLCLKO and [B, A]_ PCLK at the IC) and the rising edge of the clock as observed at the destination of the systemboard trace ([B, A]_PLLCLKI at the IC and [B, A]_PCLK at the external device), as shown in Figure 2. The IC is designed such that, for the purposes of meeting the IC AC timing requirements, if the PCLK flight time matches the PLL feedback flight time, then PCLK as observed at the destination is equivalent to the PCIdefined PCLK signal to the IC. Accordingly, the PLL feedback flight time is required to be the same as any of the PCLK trace flight times (for a bridge), within the skew limits specified by the PCI specifications for PCLK to different devices (2 ns for conventional PCI 33 MHz; 1 ns for conventional PCI 66 MHz; 0.5 ns for all PCIX mode frequencies). To improve the correlation between PCLK and the PLL feedback flight time, the delay of [B, A]_PLLCLKO and [B, A]_PCLK[4:0], relative to each other, may be altered through Dev[B, A]:0x40[PCLKDEL, PLLODEL]. However, the delay created by each increment of Dev[B, A]:0x40[PCLKDEL and PLLODEL] varies from device to device. Therefore, DevA:0x48[BDCV] provides the approximate time differential for each increment of Dev[B, A]:0x40[PCLKDEL and PLLODEL] on a given device. Thus, the values programmed into Dev[B, A]:0x40[PCLKDEL and PLLODEL] should be determined using DevA:0x48[BDCV] to adjust timing on a platform as follows: * If the PLL feedback flight time is greater than the PCLK flight time by n picoseconds, then Dev[B, A]:0x40[PCLKDEL] should be set to: n / (1250 / DevA:0x48[BDCV]). * If the PLL feedback flight time is less than the PCLK flight time by n picoseconds, then Dev[B, A]:0x40[PLLODEL] should be set to: n / (1250 / DevA:0x48[BDCV]). The result of the above equations should be rounded to the nearest integer for best accuracy. Note that only one of Dev[B, A]:0x40[PCLKDEL] or Dev[B, A]:0x40[PLLODEL] should be set to a value other than zero, never both.
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The PCLK flight time may vary with different [B, A]_PCLK frequencies (this may be a consequence of imperfect signal integrity of [B, A]_PCLK). These differences in flight time may be accounted for on a platform by: (1) for each supported [B, A]_PCLK frequency, determine the different time adjustment values required, and (2) use system BIOS to program Dev[B, A]:0x40[PCLKDEL and PLLODEL] to correct by these time adjustment values based on the [B, A]_PCLK frequency and DevA:0x48[BDCV].
PLL and clock tree
A bridge of the IC
REFCLK Delay X PLL Dev[B, A]:0x40 [PLLODEL] PLLCLKI Delay X Dev[B, A]:0x40 [PCLKDEL] PCLK source
Outgoing flops
Q
Incoming flops
D
PLLCLKO PCLK flight time
All PCI bus signals
PLL feedback flight time
PCLK dest.
External PCI device
Figure 2: Systemboard clocking.
4.3.2 Characterization
For the purposes of characterization, there is no PCI-defined PCLK signal into the IC, such as is typically used to measure setup, hold, and output valid delay times of PCI-bus signals. As shown in Figure 2, there is an unspecified skew between the PCLK outputs and PLLCLKO (Delay X). Because of this, along with the fact that the PLL feedback frequency may not be the same as PCLK, the PLL feedback signal cannot be used to characterize the IC PCI bus signals. Instead, the IC should be characterized as follows: * Make sure Dev[B, A]:0x40[PCLKDEL and PLLODEL] = 0h. * Measure the PLL feedback flight time, PLLFT, and the flight time of a [B, A]_PCLK signal connected to an external device, PCLKFT. Algebraically calculate the difference as follows: DIFFT = PLLFT - PCLKFT. Note that DIFFT may be a positive or a negative value. * Characterize the PCI-bus signals using, as a reference clock, the destination of the [B, A]_PCLK used to calculate PCLKFT. Then, adjust the measurements to obtain the correct values as follows: * Output valid delay. Algebraically subtract DIFFT from the measured output valid delay time of PCI bus signals driving out of the IC. Corrected output valid delay = Measured output valid delay - DIFFT. * Setup. Algebraically add DIFFT to the measured setup time of PCI bus signals being driven into the IC. Corrected setup time = Measured setup time + DIFFT. * Hold. Algebraically subtract DIFFT from the measured hold time of PCI bus signals being driven into the IC. Corrected hold time = Measured hold time - DIFFT.
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Difference in PCLK and PLL feedback flight time, DIFFT PCLK (observed at the destination) Adjusted PCLK (corrected for difference in flight time) Output valid delay measurement Measured output valid delay Corrected output valid delay Setup and hold time measurement Measured hold time Corrected hold time Measured setup time Corrected setup time
Figure 3: Correction for characterization.
4.3.3 Clock Gating
Internal clocks may be disabled during power-managed system states such as power-on suspend. It is required that all upstream requests initiated by the IC be suspended while in this state. To enable clock gating, DevA:0xF0[ICGSMAF] is programmed to the values in which clock gating will be enabled. Stop Grant cycles and STPCLK deassertion link broadcasts interact to define the window in which the IC is enabled for clock gating during LDTSTOP# assertions. The system is placed into power managed states by steps that include a broadcast over the links of the Stop Grant cycle that includes the System Management Action Field (SMAF) followed by the assertion of LDTSTOP#. When the IC detects the Stop Grant broadcast which is enabled for clock gating, it enables clock gating for the next assertion of LDTSTOP#. While exiting the power-managed state, the system is required to broadcast a STPCLK deassertion message. The IC uses this message to disable clock gating during LDTSTOP# assertions. This is important because an LDTSTOP# assertion is not guaranteed to occur after the Stop Grant broadcast is received. The clock gating window must be closed to ensure that clock gating does not occur during Stop Grant for LDTSTOP# assertions that are not associated with the power states specified by DevA:0xF0[ICGSMAF]. In summary, Stop Grant broadcasts with SMAF fields specified by DevA:0xF0[ICGSMAF] enable the clock gating window and STPCLK deassertion broadcasts disable the window. If LDTSTOP# is asserted while the clock gating window is enabled, then clock gating occurs. It is expected that clock gating is only employed during power-on suspend. Therefore, OS and driver software ensure that no DMA or interrupt activity occurs. In addition, it is required that there be no host accesses to the bridges or internal registers in progress from the time that LDTSTOP# is asserted for clock gating until the link reconnects after LDTSTOP# is deasserted.
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4.4
Tunnel Links
Each HyperTransport link supports CLK receive and transmit frequencies of 200, 400, 600, 800 MHz. The side A and side B frequencies are independent of each other.
4.4.1 Link PHY
The PHY includes automatic compensation circuitry and a software override mechanism, as specified by DevA:0x[E8, E4, E0]. The IC only implements synchronous mode clock forwarding FIFOs. So only the link receive and transmit frequencies specified in DevA:0x[D0, CC][FREQB, FREQA] are allowed.
4.5 PCI-X Bridges
The IC includes two 64-bit PCI-X bridges, bridge A and bridge B. Each independently support PCI-X mode or conventional PCI mode, clocks speeds of 33, 66, 100, and 133 MHz, and SHPC-compatible hot plug. Each include an IOAPIC register set. Each support 64-bit addressing in PCI-X and legacy PCI modes.
4.5.1 Tags, UnitIDs, SeqIDs And Ordering
The IC requires two HyperTransport technology-defined UnitIDs. The first UnitID applies to bridge A and the second UnitID applies to bridge B. It is contained in the following transactions: * External master requests associated with the bridge. * IOAPIC interrupt requests associated with the bridge. * Responses to host-initiated requests that enter the address space of the bridge including configuration registers (DevA registers for bridge A and DevB registers for bridge B), IO and memory space windows defined in the configuration registers of the bridge, and the base address register spaces defined by the bridge. In addition, the UnitID associated with the bridge is returned in the response to upstream requests and is used to determine the destination of the response (bridge A or bridge B). The assigned SrcTag value increments with each non-posted request from 0 to 28 and then rolls over to 0 again; the first SrcTag assigned after reset is 0. Up to 29 non-posted requests to the link may be outstanding at a time per bridge. Based on the state of Dev[B, A]:0x40[NZSEQID], the IC may or may not generate a non-zero SeqID values in the upstream link requests that result from external PCI master read requests. All bridge-sourced transactions are compliant to PCI ordering rules. As PCI transactions are converted to link transactions, they are translated as described in the link specification. Downstream non-posted link requests to a bridge that contain non-zero SeqID values are required to complete on that bus prior to initiating subsequent non-posted requests to that bus with the same SeqID value. Thus, only one downstream non-posted request with each non-zero SeqID value can be outstanding to a bridge at a time.
4.5.2 Interrupt Controllers
Each bridge supports the four PCI-defined interrupt signals, [B, A]_PIRQ[D, C, B, A]#. Assertion of these interrupt signals may be converted to link interrupt request messages as specified by the IOAPIC register space. Also, the interrupts from both bridges may be combined and output to the respective NIOAIRQ[D, C, B, A]# pins, based on Dev[B, A]:0x40[NIOAMODE].
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It is expected that system BIOS sets both Dev[B, A]:0x40[NIOAMODE] bits and that the interrupt type is determined by the way the operating system programs the interrupt mask bit (RDR[IM]; see section 5.4) of the redirection registers (non-IOAPIC-capable operating systems set the mask bits resulting in NIOAIRQ[D:A]# signal assertions; IOAPIC-capable operating systems clear the mask bits resulting in interrupt request messages to the host). The NIOAIRQ[D:A]# signals from all instances of the IC on a platform may be connected together (respectively: A to A, B to B, etc.). These four nodes are expected to be passed to the system's legacy interrupt controller to generate interrupts on behalf of the IC's bridges when IOAPIC interrupts are not supported. There is a set of IOAPIC registers associated with each bridge. They include a standard PCI function header (function 1 of each bridge) and memory mapped registers. In addition, expanded programmability of these registers is included in Dev[B, A]:0x[BC, B8]. The IOAPIC registers specify the conversion of PIRQ pin assertions to link interrupt request messages. Typically, for PCI interrupts, the redirection register (RDR; see section 5.4) is set up as follows: MT=fixed; DM=physical mode; POL=active low; TM=level sensitive; and IM=not masked. The RDR fields are mapped into link interrupt request messages as follows: RDR field IV[7:0] (interrupt vector) MT[2:0] (message type) Field in link packet Vector (bit time 5) MT[2:0] (bits[4:2] of bit time 3); MT[3] (bit[7] of bit time 3) should always be low; note that the encoding of these bits changes between the value in the RDR and the value placed into the link packet. DM (bit[6] of bit time 3) RQEOI (bit[5] of bit time 3) IntrInfo[15:8] (bit time 4); IntrInfo[55:16] should always be low.
DM (destination mode) TM (trigger mode) DEST[7:0] (destination)
DS, POL, IRR, and IM from the RDR are not included in the link interrupt packet. The state of PASSPW and INTRINFO[55:24, 7] from the IDRDR register (see Dev[B, A]:0x[BC, B8]) are also passed along in the link interrupt packet. If RDR[TM]=level sensitive for the interrupt request, then the IRR register is set when the interrupt is detected. After the interrupt request message is sent to the host, the host is required to generate an EOI broadcast message when finished with that interrupt. IRR is cleared in any RDRs (in either bridge) with IDRDR/RDR fields that match the IntrInfo fields of the EOI broadcast as follows: IntrInfo[15:8] 00h 01h-FFh Match fields IntrInfo[31:16] = {IDRDR[31:24], RDR/IDRDR[IV]}; IntrInfo[31:8] = {IDRDR[31:24], RDR/IDRDR[IV], RDR/IDRDR[DEST]};
If the interrupt signal is still asserted when the corresponding RDR logic receives an IRR-clearing EOI, then IRR is set again immediately and a new interrupt request message is sent. If the interrupt signal is deasserted near the time the corresponding IRR-clearing EOI is received, then it is undefined whether an additional interrupt request message is sent. If RDR[TM]=edge sensitive, then the state of the IRR bit is not specified and the RDR logic for that interrupt does not observe EOIs. Each RDR in the IC operates independently. If interrupts are received simultaneously by two RDR controllers, then the corresponding interrupt request messages from each are transmitted in an unspecified order.
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If LDTSTOP# is asserted near the time that an interrupt is asserted, then the corresponding interrupt request message may or may not be sent before the disconnect sequence completes. If it is not sent before the disconnect sequence completes, then it is not dropped; it is sent after the link is re-connected. External devices are required to assert PIRQ[D:A]# for at least 3 PCLK cycles in order to guarantee that the IC detects the assertion, regardless of the state of the corresponding RDR[TM] field.
4.5.2.1 Error NMI Interrupts
NMI interrupts may be generated as a result of assertions of the [B, A]_PERR# and [B, A]_SERR# signals (regardless of the source of the assertion), as enabled by Dev[B, A]:0x44[NMIEN]. These interrupt requests are generated with the following link format: PassPW=0; INTRINFO[55:24]=0000_00F8h; IV=00h; DEST=FFh; DM=0 (physical); TM=0 (edge); MT=0011b (NMI).
4.5.3 Hot Plug
Each PCI-X Bridge includes an SHPC-compliant hot plug controller that may be used to support hot plug capable conventional PCI or PCI-X slots. Strapping options on HPSOD and HPSIL# specify if hot plug is supported on bridge A and/or B. If hot plug is supported on a bridge, then all slots connected to that bridge are required to include hot plug support circuitry. With the exception of a single-slot hot plug implementation, the hot plug support circuitry includes one or more Texas Instruments TPS2340 hot plug power controllers, power switches, and associated slot isolation switches to provide electrical isolation for most of the slot signals. For a single-slot hot plug implementation, the IC provides the bus isolation function; therefore only the TI TPS2340 hot plug power controller and the power switches are required. Each bridge supports a maximum of 4 slots when hot plug mode is enabled. The IC's hot plug controller is designed to interface with the TI TPS2340 hot plug power controller. Each TI TPS2340 controls two slots and provides two separate sets of isolation switch controls. TI TPS2340 controllers may be cascaded to support additional slots. A single TI TPS2340 hot plug power controller cannot be shared across bridge A and bridge B. The IC is connected to the power controller via a serial bus. One serial interface supports the power controllers for bridge A and bridge B.
4.5.3.1 Multi-slot Hot Plug
If multiple hot plug slots are supported on a bridge, isolation switches are required for each slot to provide electrical isolation. Each TI TPS2340 hot plug power controller provides two pairs of isolation switch control signals, BUSENx# and CLKENx#, to control the state of the switches.
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Link
A PCI-X A
PCIX
bridge A Hot plug serial bus controller 1 Power controllers 1
PCI-X
2
3
4 Power and isolation control
SHPC SHPC
2
3
4
B
bridge B
B
Link
PCIX
- Isolation Switch
Figure 4: System diagram for multiple hot plug slots on a bridge.
The following table associates the hot plug power controller's isolation switch control signal with the IC's slot signals. Power controller signal Slot signals isolated BUSENx# [B, A]_ACK64#, [B, A]_AD[63:0], [B, A]_CBE_L[7:0], [B, A]_DEVSEL#, [B, A]_FRAME#, [B, A]_GNT#[3:0], [B, A]_IRDY#, [B, A]_PAR, [B, A]_PAR64, [B, A]_PERR#, [B, A]_PIRQ[A, B, C, D]#, [B, A]_REQ#[3:0], [B, A]_REQ64#, [B, A]_SERR#, [B, A]_STOP#, [B, A]_TRDY#. [B, A]_PCLK[3:0], [B, A]_M66EN.
CLKENx#
Table 2.
Signal isolation groups.
The TI TPS2340 hot plug power controller controls RESET# to the slot. The IC's [B, A]_PRESET# signals are connected to the TI TPS2340 hot plug power controller's serial interface control signal, SORR#. Some operating systems require that each configuration-space bus number provide a separate PME# signal to a general-purpose set of PME# status bits provided by the platform system management logic. The IC's [B, A]_PME# signals are associated with the power management configuration registers Dev[B, A]:0x[9C:98], both of which are observed by software on the primary side of the PCI bridges and are therefore on the same bus number. Therefore, the IC's two [B, A]_PME# pins may be connected together and passed to the platform system management logic. The slots are observed by software on the IC's secondary bus, which is a different bus number from the primary side. Therefore, the each bridge should provide a separate PME# signal to the platform system management logic, that logically connects to all the slots behind the bridge. The TI TPS2340 hot plug power controller's PME# inputs connects to the PME# signal of each hot plug slot. Its PME# outputs for one bridge should be connected together and passed to the platform system management logic.
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3.3V 3.3VA The IC A_PME# Bridge PME# Power Controller PME#(n) PMEO# PME#(n+1)
Bridge A, Slot (n)
Bridge A, Slot (n+1)
B_PME#
Bridge A, Slot (n+2) Power Controller PME#(n+2) PMEO# PME#(n+3) Bridge A, Slot (n+3)
Platform system management logic
Figure 5: System diagram of PME# signals.
The slot signals that are used to communicate the speed, capability (M66EN and PCIXCAP), and presence of an adapter card (PRSNT[1:2]#) are isolated from the other slots in a hot plug implementation. These signals are directly connected from the slot connector to their associated TI TPS2340. The state of these signals is provided to the IC through the serial interface. The IC, in turn, makes the state of these signals available to system software. The [B, A]_PCIXCAP and [B, A]_M66EN pins on the IC are not used for sensing speed and mode. The IC's [B, A]_PCIXCAP pins are left unconnected. The connection and function of the M66EN signal is unique in a hot plug implementation for two reasons: (1) M66EN is driven as an output of the IC; (2) its isolation switch control is driven by CLKEN# rather than BUSEN# (unlike other PCI/PCI-X control signals). In a hot plug configuration, the IC's [B, A]_M66EN pin is configured as an open-drain output. It is driven low by the IC if it is determined that the bus is to run at 33MHz (conventional PCI mode), as indicated in SHPC[B, A]:x10[MODE].
CLKEN(n)# 3.3V Slot Power
The IC
[B, A]_M66EN Slot (n)
M66EN(n) Power Controller CLKEN(n+1)# 3.3V Slot Power
- Isolation Switch
Slot (n+1)
M66EN(n+1)
Figure 6: System diagram of M66EN signals.
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The process of setting the state of [B, A]_M66EN when the bridge is initialized is: (1) the TI TPS2340 hot plug power controller is programmed to apply power to the slots via the SHPC[B, A]:14 power-only all slots command; (2) software observes the state of the speed capability signals for the slots by reading SHPC[B, A]:[30:24][M66_CAP]; (3) software issues the SHPC[B, A]:14 set bus segment speed/mode command, which immediately places the appropriate state on [B, A]_M66EN out of the IC; (4) software issues the SHPC[B, A]:14 slot enable command, which results in the assertion of CLKENx# so that [B, A]_M66EN out of the IC is enabled to the slot.
[B, A]_PRESET# PWREN CLKENx# BUSENx# Most slot signals [B, A]_PCLK[3:0] Slot power Slot RESET# 120-150 ms 60-90 ms About 22 PCLK cycles Slot enable command sequence 6-10 us 6-10 us Valid Valid
About 22 PCLK cycles Slot disable command sequence
* Signal states are shown from the perspective of the pins of the IC; the perspective from the slot is different due to the isolation switches controlled by CLKENx# and BUSENx#. * "Most slot signals" includes the signals controlled by BUSENx#. * M66EN is driven low after RESET# is asserted; after that, its state is determined by the bus speed and mode.
Figure 7: Multi-slot hot plug enable/disable sequence.
4.5.3.2 Single-Slot Hot Plug
Isolation switches are not required if the bridge supports a single hot plug slot. The IC provides the isolation function by controlling the slot signals appropriately. The TI TPS2340 hot plug power controller is still required.
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AMD-8131TM PCI-X Tunnel Data Sheet
Link
A PCI-X A
PCIX
bridge A SHPC SHPC
PCI-X
Hot plug serial bus controller
Power Controller Power Controller PCIX
bridge B B Link
B
Figure 8: Single-slot hot plug system diagram.
Single-slot hot plug support is enabled for each bridge through strapping options on HPSIC and B_GNT2#. The state of these strapping options are observable through Dev[B, A]:0x40[HPSSS#]. The IC drives all slot signals low throughout the duration of a cold reset and continues to do so until after the TI TPS2340 hot plug power controller applies power to the adapter. The IC interprets the SHPC commands to control the signals in the power-only, slot enable, and slot disable sequences. The following figure shows how signals are controlled by the IC during the sequence initiated by the slot enable command and the slot disable command.
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[B, A]_PRESET# PWREN CLKEN BUSEN Most slot signals [B, A]_PCLK0 Tristate M66EN [B, A]_REQ0# Slot power Slot RESET# 120-150 ms 60-90 ms About 22 PCLK cycles 6-10 us 6-10 us Valid Valid 1 if conventional PCI, 66 MHz; otherwise 0 Observed as an input Tristate
Tristate; input ignored
Tristate; input ignored
About 22 PCLK cycles
Slot enable command sequence
Slot disable command sequence
* CLKEN and BUSEN represent the approximate times in which the TI TPS2340 change the state of its CLKENx# and BUSENx# signals. However, these signals out of the TI TPS2340 do not directly control the above signals. * PWREN represents the times in which the TI TPS2340 enables power to the slot. * "Most slot signals" includes the signals controlled by BUSENx# in section 4.5.3.1.
Figure 9: Single-slot hot plug enable/disable sequence.
The IC's [B, A]_PCIXCAP pins are left unconnected. PCIXCAP and PRSNT[1:2]# from the slot are connected to the TI TPS2340 hot plug power controller. The IC's [B, A]_M66EN pins are connected directly to the slot with a pull-up resistor to the slot power plane. This pin remains tri-stated until the SHPC enables the slot so the state provided by the card in the slot may be observed. This pin is driven low by the IC if it is determined that the bus is to run at 33MHz in conventional PCI mode.
Slot Power Power Controller Slot (n)
The IC
[B, A]_M66EN
M66EN(n)
Figure 10: Single-slot hot plug M66EN connections.
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The process of setting the state of [B, A]_M66EN when the bridge is initialized is: (1) the TI TPS2340 hot plug power controller applies power to the slot via the SHPC[B, A]:14 power-only command; (2) software observes the state of the speed capability signals for the slot by reading SHPC[B, A]:[24][M66_CAP]; (3) software issues the SHPC[B, A]:14 set bus segment speed/mode command which determines the state of [B, A]_M66EN (but the state of the pins does not change); (4) software issues the SHPC[B, A]:14 slot enable command and [B, A]_M66EN may be driven low at the same time that CLKENx# is asserted out of the TI TPS2340. The IC is designed such that only active-low interrupts (from [B, A]_PIRQ[D:A]#) are supported when in single-slot support mode, while the slot is not enabled. If the IOAPIC is programmed for active high interrupts in this mode, then spurious interrupt requests are generated.
4.5.3.3 Serial Interface
The hot plug serial interface operates at 8.33 MHz. It converts SHPC commands to a serial format to communicate with the TI TPS2340 hot plug power controllers. In addition, it is used to read status information from the TI TPS2340 hot plug power controllers and update the IC's SHPC status registers accordingly. The following table identifies two different groups of serial interface signals. Common Serial signals are connections between the IC and all TI TPS2340 hot plug power controllers (shared across both PCI/PCI-X bridges). Bridge specific signals are connections between the IC and only those TI TPS2340 hot plug power controllers connected to a particular bridge. (For additional information, see TI TPS2340A Dual-slot PCI Hot-Plug Power Controller.)
The IC
B_HPSORR#, B_HPSOLC, B_HPSORLC A_HPSORR#, A_HPSOLC, A_HPSORLC
TI TPS2340 Bridge A Slots 1 & 2
HPSOD A_HPSID SODI SODO SIDO SIDI
TI TPS2340 Bridge A Slots 3 & 4
SODI SODO SIDO SIDI
TI TPS2340 Bridge B Slots 1 & 2
SODI SODO SIDO SIDI
TI TPS2340 Bridge B Slots 3 & 4
SODI SODO SIDO SIDI
B_HPSID HPSIC, HPSOC, HPSIL# RESET#
HPSOR# = system RESET# signal
Figure 11: Hot plug serial interface connections.
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Common Serial Signals HPSIC. Output. This 8.33 MHz clock is used to shift serial data from the TI TPS2340 to the IC over [B, A]_HPSID. Each bit is captured by the IC on the rising edge of this clock. HPSIL#. Output. This signal is used to specify the start of an input data frame and the data type--or channel number--being shifted into the IC over [B, A]_HPSID. HPSOC. Output. This 8.33 MHz clock is use to shift serial data from the IC to the TI TPS2340 over HPSOD. Each bit is captured by the TI TPS2340s on the rising edge of this clock. HPSOD. Output. This is the serial data shifted from the IC to the TI TPS2340s, clocked by HPSOC. HPSOR#. The TI TPS2340's SOR# input is connected to the same platform reset signal as is used for the IC's RESET#. When SOR# is asserted, all of the slot control outputs of the TI TPS2340 are reset except the slot reset signal, RESETx# (which is reset by [B, A]_HPSORR#). Bridge Specific Serial Signals [B, A]_HPSID. Input (multiplexed with [B, A]_PCLK4). This is the serial data shifted into the IC from the TI TPS2340s, clocked by HPSIC. [B, A]_HPSOLC. Output (multiplexed with [B, A]_REQ4#). This signal is used to load the state of the serial data shifted into the TI TPS2340 over HPSOD into output latches. All outputs of the TI TPS2340 are updated on the rising edge of [B, A]_HPSOLC, except the slot reset signal, RESETx# (which is updated by [B, A]_HPSORLC). [B, A]_HPSORLC. Output (multiplexed with [B, A]_GNT4#). This signal is used to load the state of the slot reset signals shifted into the TI TPS2340 over HPSOD into output latches. RESETx# out of the TI TPS2340 is updated on the rising edge of [B, A]_HPSORLC. [B, A]_HPSORR#. Output (multiplexed with [B, A]_PRESET#). This signal is used to reset the state of the TI TPS2340's output latches that drive RESETx# (to low). 4.5.3.3.1 Serial Data From The Power Controllers To The IC
Channel 00b interrupt-capable data and channel 01b non-interrupt-capable data is shifted into the IC from the TI TPS2340 over [B, A]_HPSID using HPSIC as the clock. This data is continuously shifted into the IC, toggling between channels 00b and 01b. HPSIL# controls the start of each block and specifies the channel number. HPSIL# transitions after the falling edge of HPSIC. The tables below show how the data for 4 slots are transferred into the IC. However, the actual number of slots transferred is limited to the maximum of the number of slots on bridge A or bridge B.
Clock # 0 1 2 3 4 5 6 7 8 HPSIL# 1 0 (start) 0 (chan[0]) 0 (chan[1]) 1 1 1 1 1 First TPS2340 SWA signal (1=MRL sensor is open) passed to SHPC[B, A]:24[MRLS]. First TPS2340 BUTTONA# signal (1=attention button is being pressed; this is an inversion of the state as it is placed onto the TPS2340 BUTTONA# pin) passed to SHPC[B, A]:24[AB]. First TPS2340 power fault state (0=power fault is detected) passed through an inverter to SHPC[B, A]:24[PF]. First TPS2340 PRSNT2A# signal passed to SHPC[B, A]:24[PRSNT1_2]. Data out of TI TPS2340 over [B, A]_HPSID after rising edge of HPSIC
Table 3: Channel 00b, interrupt capable serial hot plug data to the IC. 28
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9 12:10 17:13 20:18 25:21 28:26 33:29
1 1 1 1 1 1 1
First TPS2340 PRSNT1A# signal passed to SHPC[B, A]:24[PRSNT1_2]. Reserved. First TPS2340 slot B signals passed to SHPC[B, A]:28[PRSNT1_2, PF, AB, MRLS]. Reserved. Second TPS2340 slot A signals passed to SHPC[B, A]:2C[PRSNT1_2, PF, AB, MRLS]. Reserved. Second TPS2340 slot B signals passed to SHPC[B, A]:30[PRSNT1_2, PF, AB, MRLS].
Table 3: Channel 00b, interrupt capable serial hot plug data to the IC.
Clock # 1 2 3 4 5 6 7 8 12:9 16:13 20:17 24:21 28:25 32:29 HPSIL# 0 (start) 1 (chan[0]) 0 (chan[1]) 1 1 1 1 1 1 1 1 1 1 1 First TPS2340 M66ENA signal passed to SHPC[B, A]:24[M66_CAP]. First TPS2340 PCIXCAPA# signal passed to SHPC[B, A]:24[PCIX_CAP]. First TPS2340 PCIXCAPA# signal passed to SHPC[B, A]:24[PCIX_CAP]. First TPS2340 auxiliary power fault state (not observable). Reserved. First TPS2340 slot B signals passed to SHPC[B, A]:28[M66_CAP, PCIX_CAP]. Reserved. Second TPS2340 slot A signals passed to SHPC[B, A]:2C[M66_CAP, PCIX_CAP]. Reserved. Second TPS2340 slot B signals passed to SHPC[B, A]:30[M66_CAP, PCIX_CAP]. Data out of TI TPS2340 over [B, A]_HPSID after rising edge of HPSIC
Table 4: Channel 01b, non-interrupt capable serial hot plug data to the IC.
4.5.3.3.2 Serial Data From The IC To The Power Controllers
Serial data is transferred over HPSOD to the TI TPS2340s, where it is stored, using HPSOC as the clock. The state of the outputs and control signals stored in the power controller do not change until a rising edge of [B, A]_HPSORLC, in the case of RESETx#, and [B, A]HPSOLC, in the case of the rest of the signals. The data is shifted whenever there is a need to change the state of these signals, normally as a result of a command to SHPC[B, A]:14. The IC shifts out four slots worth of data, regardless of how many slots are actually attached to the bridge, followed by pulses on [B, A]_HPSORLC and [B, A]HPSOLC. HPSOD transitions after the falling edge of HPSOC.
Clock # 1 2 3 4 5 Data out of the IC over HPSOD during the rising edge of HPSOC Second TPS2340 slot B power enable state. 1=Power enabled to the slot. Second TPS2340 CLKENB state. 1=CLKEN signals enabled. Second TPS2340 BUSENB state. 1=BUSEN signals enabled. Second TPS2340 RESETB# state. Second TPS2340 PWRLEDB# state. 1=Turn on power LED.
Table 5: Serial hot plug data from the IC to the power controller. 29
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6 8:7 14:9 16:15 22:17 24:23 30:25
Second TPS2340 ATTLEDB# state. 1=Turn on attention LED. Reserved. Second TPS2340 slot A control signals and outputs. Reserved. First TPS2340 slot B control signals and outputs. Reserved. First TPS2340 slot A control signals and outputs.
Table 5: Serial hot plug data from the IC to the power controller.
4.5.3.4 SHPC Interrupts, Events, And Errors
Under the conditions described by SHPC[B, A]:20, the IC may assert [B, A]_PIRQA#, [B, A]_PME#, or indicate a system error on the links.
4.5.3.5 Reset To Hot Plug Slots
The state of reset for each hot plug slot is passed from the SHPC controller, through the serial bus, to the TI TPS2340 hot plug power controllers, where it is driven to the slots. The PCI requirement for a delay between the rising edge of RST# and the first configuration access is not enforced by the IC with hardware; it is expected that this requirement be enforced through software. The hot plug software driver may be used to inhibit configuration accesses to a slot after commands that result in deassertions of RST# to the slot are executed. The set bus speed/mode command and the enable slot command result deassertions of RST#. Each of these commands complete in less than 250 milliseconds after being received by the IC. The PCI requirement results in a 0.5 to 1.0 second period (depending on the bus frequency) after the deassertion of RST# during which configuration accesses to the slot are not allowed. Therefore, if the hot plug driver inhibits configuration accesses to the slot for 1.25 seconds after these commands are sent to the IC, the PCI requirement should be satisfied.
4.5.4 PCI-X PHY Compensation Update
The PCI-X PHY calculated compensation values may change at any time. These may be altered, based on DevA:0x[54, 50], before being passed on to the PHY. The IC ensures that the PCI-X bridges are idle when new values are passed to the PHY. The following logic is implemented to accomplish this: * Shortly after reset, or whenever a new value is written to DevA:0x[54, 50], and every 16 milliseconds thereafter, the IC determines if any of the values that are to be present to the PHY have changed and therefore need to be updated. If the values have not changed, no action takes place until the next 16 millisecond period passes and the values are checked again. * If the compensation values are to be updated, then the logic request control over the bridges for the compensation update. * The logic ensures that the bridges are idle for at least two PCLK cycles before and 4 PCLK cycles after the new values are passed to the PHY. During these six or more PCLK cycles, the IC drives the value of 0123_4567_89AB_CDEFh onto [B, A]_AD[63:0].
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4.5.5
Transactions Claimed By The Bridges
The bridges claim no upstream transactions. They claim the following downstream transactions: * All memory and IO space specified by Dev[B, A]:0x[30:1C]. * All configuration cycles to the implemented functions of DevA or DevB (see section 5.1.2). * All configuration cycles to buses behind bridge A and bridge B. * All EOI broadcasts are passed to the IOAPIC. * All Stop Grant and STPCLK broadcasts are observed for clock gating (see section 4.3.3). * If DevA:0x48[COMPAT]=1, then all memory space, IO space, and interrupt acknowledge packets in which the COMPAT bit is set are claimed and passed to bridge A. Per the link protocol, when the COMPAT bit is set in the transaction and DevA:0x48[COMPAT]=0, then the IC never claims the transaction. Such transactions are automatically passed to the other side of the tunnel (or master aborted if the IC is at the end of the chain).
4.5.6 Various Behaviors
* Cacheline-wrap mode is not supported. If a transaction is initiated that indicates this protocol, it is disconnected at the first data phase. * Downstream special cycles that are encoded in configuration cycles to device 31 of the bridge's secondary bus number (per the PCI-to-PCI bridge specification) are translated to special cycles on the bridge. * Secondary-bus configuration cycles are never claimed by the IC (including configuration cycles to device 31 in which special cycles are encoded per the PCI-to-PCI bridge specification). * In the translation from type 1 link configuration cycles to secondary bus type 0 configuration cycles, the IC converts the device number to an IDSEL AD signal as follows: device 0 maps to AD[16]; device 1 maps to AD[17]; and so forth. Device numbers 16 through 31 are not valid. * Transactions that cross address space boundaries, as defined by the window configuration registers, Dev[B, A]:0x[30:1C], result in undefined behavior. * If the bridge is in PCI-X mode and an upstream memory read or write request is issued with the No Snoop bit of the attribute field set high, then the coherent bit of the corresponding link read sized or write sized requests is low. The coherent bit is high for all other link requests, including all conventional PCI transactions and IO commands. The No Snoop field bit of the attribute field is always low in downstream requests to the PCI-X bridge. * The following tables show the relationship between PCI-X transactions in which the relaxed ordering bit is set and link packets: Downstream link transaction Corresponding PCI-X transaction A read request in which bit[3] of the command field (response may pass posted write) is set. A response in which PassPW is set. A posted memory write in which the PassPW bit is set. Relaxed ordering bit of the attribute field is set. Relaxed ordering bit of the attribute field is set. No effect; the relaxed ordering bit is zero regardless of the state of the PassPW bit.
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Upstream PCI-X transaction
Corresponding link transaction
A read request in which the relaxed ordering bit of the Bit[3] of the command field (response may pass attribute field is set. posted write) in the read request is set. A split completion in which the relaxed ordering bit of PassPW is set in the response. the attribute field is set. An immediate response to a downstream link read request in which bit[3] of the command field (response may pass posted write) is set. PassPW is set in the response (even though there is no attribute field associated with the PCI-X response).
A posted memory write in which the relaxed ordering No effect; PassPW is zero regardless of the state of bit of the attribute field is set. the relaxed ordering bit. * If there is a downstream PCI-X request that results in a device-specific error in the completion message, then the response passed to the link indicates a target abort (error bit set; NXA clear). * When the IC asserts [B, A]_DEVSEL#, it does so using the medium decoding clock in conventional PCI mode and the "B" decoding clock in PCI-X mode. * If there is a link transaction to IO-space that targets a bridge and that crosses a naturally aligned DWORD boundary, then the IC does not send the transaction to the bus and the link response is a master abort (error bit set; NXA set).
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4.5.7
Error Conditions And Handling
The tables below describe how the IC responds to error conditions. Error handling for secondary bus responses to the IC. Response from the secondary bus Behavior of the IC Signal master abort (DEVSEL not asserted); Dev[B, A]:0x3C[MARSP]=0. Signal master abort (DEVSEL not asserted); Dev[B, A]:0x3C[MARSP]=1; non-posted request. Signal master abort (DEVSEL not asserted); Dev[B, A]:0x3C[MARSP]=1; posted request. * Link response with data of all F's for non-posted transaction. * Posted transaction is discarded. * Dev[B, A]:0x1C[RMA]=1. * Link response with data of all F's and the error bit set. * Dev[B, A]:0x04[STA]=1. * Dev[B, A]:0x1C[RMA]=1. * Posted transaction is discarded. * Dev[B, A]:0x1C[RMA]=1. * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Outgoing links are flooded with sync packets.
Signal master abort (DEVSEL not asserted) * Split completion transaction is discarded. for a split completion message to the sec- * Dev[B, A]:0x1C[RMA]=1. ondary bus. * Dev[B, A]:0xA0[SCD]=1. * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Outgoing links are flooded with sync packets. Signal target abort; non-posted request. * Link response with data of all F's and the error bit set. * Dev[B, A]:0x04[STA]=1. * Dev[B, A]:0x1C[RTA]=1. * Remainder of posted transaction is discarded. * Dev[B, A]:0x1C[RTA]=1. * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Outgoing links are flooded with sync packets. Link response with data of all F's and the error bit set. * Split completion transaction is discarded. * Dev[B, A]:0x1C[RTA]=1. * Dev[B, A]:0xA0[SCD]=1. * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Outgoing links are flooded with sync packets.
Signal target abort; posted request.
Signal target abort for a split completion message to the secondary bus.
Split completion error; PCI-X bridge error; * Link response with data of all F's for non-posted transaction. master abort Dev[B, A]:0x3C[MARSP]=0. * Dev[B, A]:0x1C[RMA]=1. Split completion error; PCI-X bridge error; * Link response with data of all F's and the error bit set. master abort Dev[B, A]:0x3C[MARSP]=1. * Dev[B, A]:0x04[STA]=1. * Dev[B, A]:0x1C[RMA]=1. Split completion error; PCI-X bridge error; * Link response with data of all F's and the error bit set. target abort. * Dev[B, A]:0x04[STA]=1. * Dev[B, A]:0x1C[RTA]=1.
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Split completion error; PCI-X bridge error; * A TargetDone response is returned with no error indicated. write data parity error. * If Dev[B, A]:0x3C[PEREN]=1, then: * Dev[B, A]:0x1C[MDPE]=1. Split completion error; completer error; byte count out of range. Split completion error; completer error; split write data parity error. Split completion error; completer error; device specific error. * Link response with data of all F's and the error bit set. * Dev[B, A]:0x04[STA]=1. * A TargetDone response is returned with no error indicated. * If Dev[B, A]:0x3C[PEREN]=1, then: * Dev[B, A]:0x1C[MDPE]=1. * Link response with data of all F's and the error bit set. * Dev[B, A]:0x04[STA]=1.
Error handling error conditions detected by the IC. Error condition to IC Behavior of the IC Link response to the bridge indicates a mas- * Split completion indicates a master abort PCI-X bridge error. ter abort; PCI-X mode. * Dev[B, A]:0x04[RMA]=1. Link response to the bridge indicates a mas- * Data of all F's is returned. ter abort; conventional PCI mode; Dev[B, * Dev[B, A]:0x04[RMA]=1. A]:0x3C[MARSP]=0. Link response to the bridge indicates a mas- * Target abort signaled on the PCI bus. ter abort; conventional PCI mode; Dev[B, * Dev[B, A]:0x04[RMA]=1. A]:0x3C[MARSP]=1. * Dev[B, A]:0x1C[STA]=1. Link response to the bridge indicates a tar- * Signal target abort on PCI bus; the rest of the data associated get abort in conventional PCI mode. with transaction is discarded. * Dev[B, A]:0x04[RTA]=1. * Dev[B, A]:0x1C[STA]=1. Link response to the bridge indicates a tar- * Split completion indicates a target abort PCI-X bridge error; get abort in PCI-X mode. the rest of the data associated with the PCI-X transaction is discarded. * Dev[B, A]:0x04[RTA]=1. * Dev[B, A]:0x1C[STA]=1. Parity error is detected in address or * Dev[B, A]:0x1C[DPE]=1. attribute phase of a transaction from the sec- * If [B, A]:0x3C[PEREN]=1, then: ondary bus to the IC. * The IC claims the transaction and terminates with a target abort; and * Dev[B, A]:0x1C[STA]=1; and * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Both links are flooded with sync packets. Parity error detected in the data phase of a * Dev[B, A]:0x1C[DPE]=1. split completion message from the second- * If [B, A]:0x3C[PEREN]=1, then: ary bus to the IC. * The IC claims the transaction and terminated with a target abort; and * Dev[B, A]:0x1C[MDPE]=1; and * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Both links are flooded with sync packets.
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Parity error detected in the data phase of a split completion transaction from the secondary bus to the IC.
* The data is passed to the link as read by the IC. * Dev[B, A]:0x1C[DPE]=1. * If [B, A]:0x3C[PEREN]=1, then: * Dev[B, A]:0x1C[MDPE]=1; and * [B,A] PERR# is asserted; and * If Dev[B, A]:0x44[NMIEN]=1, then: * NMI is generated.
Parity error is detected in the data phase of a * The data is passed to the link as read by the IC. read response from the secondary bus to the * Dev[B, A]:0x1C[DPE]=1. IC. * If Dev[B, A]:0x3C[PEREN]=1, then: * Dev[B, A]:0x1C[MDPE]=1; and * [B, A]_PERR# is asserted; and * If Dev[B, A]:0x44[NMIEN]=1, then: * NMI is generated. [B, A]_PERR# is detected asserted after a * If Dev[B, A]:0x44[NMIEN]=1, then: data phase of a read split completion or read * NMI is generated. immediate response from the IC to the secondary bus. [B, A]_PERR# is detected asserted after the * A TargetDone response is returned with no error indicated. data phase of a non-posted write from the * If Dev[B, A]:0x3C[PEREN]=1, then: IC to the secondary bus. * Dev[B, A]:0x1C[MDPE]=1. * If Dev[B, A]:0x44[NMIEN]=1, then: * NMI is generated. Parity error is detected in the data phase of a * The data is passed to the link as received by the IC. posted or non-posted write from the second- * Dev[B, A]:0x1C[DPE]=1. ary bus to the IC. * If Dev[B, A]:0x3C[PEREN]=1, then: * [B, A]_PERR# is asserted; and * If Dev[B, A]:0x44[NMIEN]=1, then: * NMI is generated. [B, A]_PERR# is detected asserted after the * If Dev[B, A]:0x3C[PEREN]=1, then: data phase of a posted write from the IC to * Dev[B, A]:0x1C[MDPE]=1; and the secondary bus. * If Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Both links are flooded with sync packets. * If Dev[B, A]:0x44[NMIEN]=1, then: * NMI is generated. [B, A]_SERR# or [B, A]_SHPC_SERR assertion is detected. * Dev[B, A]:0x1C[RSE]=1. * If both Dev[B, A]:0x04[SERREN]=1 and Dev[B, A]:0x3C[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Both links are flooded with sync packets. * If Dev[B, A]:0x44[NMIEN]=1, then: * NMI is generated.
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Link CRC error is detected.
* Appropriate bit of DevA:0x[C8:C4][CRCERR]=1. * If both Dev[B, A]:0x04[SERREN]=1 and DevA:0x[C8:C4][CRCFEN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Outgoing links are flooded with sync packets. * Outgoing links are flooded with sync packets. * Transaction is thrown out. * Dev[B, A]:0x3C[DTS]=1. * If both Dev[B, A]:0x3C[DTSE]=1 and Dev[B, A]:0x04[SERREN]=1, then: * Dev[B, A]:0x04[SSE]=1; and * Outgoing links are flooded with sync packets. * The transaction is terminated by signaling a target abort. * Dev[B, A]:0x1C[STA]=1.
Link incoming sync flood is detected. Discard timer time out (only in conventional PCI mode).
The IC detects an illegal address/byte enable combination during the address phase of a transaction from the secondary bus to the IC.
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4.6 4.6.1
Performance-Related Information Bandwidth Percentage
One important measure of the IC performance is the ratio of data bandwidth that can pass over the PCI bus to the theoretical maximum. This is called the bandwidth percentage or BWP. The theoretical maximum is defined as the product of the bus width and the bus frequency. This does not account for clocks that are required by the protocol for purposes other than data transfer, e.g., address phases. The IC is implemented in such a way that when external PCI devices generate long data length transactions, the clocks that are lost to the protocol become less significant to the BWP. If external PCI devices generate many small data length transactions, then this acts to reduce the BWP. Memory read requests and write requests from external PCI masters have different BWP characteristics. Generally speaking, memory writes are handled with high BWP values because they use the link posted channel. Write requests are converted from PCI protocol to link protocol by the IC efficiently. Memory reads, however, use the link non-posted channel. The response to each read request cannot be provided to the PCI bus until it is available. The time required for the response to reach the PCI bus includes the time for the request to pass from the PCI bus to the IC and from the IC to the host, and for the response to pass from the host back to the IC and from the IC out to the PCI bus. If there are other tunnel devices between the IC and the host, these will act to further increase this latency. If, for example, a single PCI master generates a pattern of (1) a single-cacheline (64 bytes) memory read request, (2) a burst of the response data to the PCI bus, (3) repeat, and that is the only activity on the bus, then the BWP is low; there will be many idle clocks, waiting for the response, between each cacheline burst on the PCI bus. BWP may be improved by support for multiple, simultaneous read requests. In conventional PCI mode and PCI-X mode, the IC supports up to 8 independent PCI read requests simultaneously, per bridge. If, as in the example above, two masters generate a pattern of (1) a single-cacheline memory read request, (2) a burst of the response data to the PCI bus, (3) repeat, then, the total BWP may roughly double. In PCI-X mode, long data length reads result in a high BWP because the time spent transferring data on the PCI bus becomes large compared to the time waiting for the response data. In conventional PCI mode, the size of the read requests is not provided by the protocol. Instead, the memory read command code provides hints as to the amount of data that may be required by the external PCI master. Dev[B, A]:0x4C specifies the number of cachelines that are prefetched from the host based on the PCI command code. The initial prefetch value in this register should be balanced based on the requirements of the system. If it is too high (such that the master does not use all the data), then unnecessary memory read requests are generated and the corresponding data is thrown out. If it is too low, then the response latency is not well covered, resulting in a low BWP. The logic for each bridge can generate up to 29 link read requests, each request for up to 64 bytes (one cacheline) of data, in support of read commands generated by external PCI-bus devices. These link requests are generated by the IC in the order in which they are received from the PCI bus. However, the responses to these PCI read requests may be provided on the PCI bus in a different order from the order in which the requests were received by the IC; this reordering depends on a number of factors including when the data for each request is provided by the host and if the master is ready to accept the data. The following table provides some bandwidth percentages measured in an ideal-model simulation environment. This data is provided for guidance, with no guarantee that it represents the exact behavior of a real-world system design. For these measurements:
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* All simulations are run while multiple, simultaneous requests are being processed. Read measurements are taken on the PCI bus, after host latency has passed, such that host latency does not affect the results. * No other traffic is present except the requests associated with the measurements. * Conventional PCI numbers presume that prefetching is enabled in continuous mode and the initial prefetch value is programmed to be high enough to cover the round-trip latency of the response. Thus, all cachelines of the response to a request can be burst onto the PCI bus without interruption. * These results apply to all PCI-bus frequencies supported by the IC. * Number of cachelines specifies the number of 64-byte cachelines requested by the PCI master. Note that the overhead is the same, regardless of the number of cachelines requested. * Total clocks specifies the number of clocks from the end of one burst, associated with one request, to the end of the next burst, associated with another request. It is the sum of the burst clocks and overhead clocks. * Overhead clocks specifies the number of PCI bus clocks during which there is no data transfer due to PCI protocol overhead and overhead inherent to the IC. * Data burst clocks specifies the number of PCI bus clocks during which data is transferred. * BWP is bandwidth percentage. BWP=(BurstClks/TotalClks)*100.
Type Number of PCI bus cachelines width 2 8 32 Conventional PCI reads from host memory 2 8 32 PCIX writes to host memory 2 8 32 PCIX reads from host memory 2 8 32 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit 32 bit 64 bit Total clocks 37 21 133 69 517 261 39 23 135 71 519 263 41 25 137 73 521 265 41 25 137 73 521 265 Overhead clocks 5 5 5 5 5 5 7 7 7 7 7 7 9 9 9 9 9 9 9 9 9 9 9 9 Data burst clocks 32 16 128 64 512 256 32 16 128 64 512 256 32 16 128 64 512 256 32 16 128 64 512 256 BWP
Conventional PCI writes to host memory
86 76 96 93 99 98 82 70 95 90 99 97 78 64 93 88 98 97 78 64 93 88 98 97
Table 6: Bandwidth percentages.
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4.6.2
Latency
The following table provides some latency values measured in an ideal-model simulation environment. This data is provided for guidance, with no guarantee that it represents the exact behavior of a real-world system design. For these measurements: link A is 16 bits, 800 MHz; link B is 8 bits, 800 MHz; the host is connected to link A; no other traffic is present except the transactions described; latency is measured from the first clock in which the transaction is clocked into the IC until the first clock in which the transaction is clocked out of the IC.
Latency (ns) Description 75-85 65-75 225-235 300-310 135-145 180-190 180-190 180-190 130-140 145-155 110-120 135-145 Read response from link A to link B. Read response from link B to link A. Read request from conventional PCI, 33 MHz, any width (32 or 64 bit), to link A. Read response from link A to conventional PCI, 33 MHz, any width. Read request from conventional PCI, 66 MHz, any width, to link A. Read response from link A to conventional PCI, 66 MHz, any width. Read request from PCI-X, 66 MHz, any width, to link A. Read response from link A to PCI-X, 66 MHz, any width. Read request from PCI-X, 100 MHz, any width, to link A. Read response from link A to PCI-X, 100 MHz, any width. Read request from PCI-X, 133 MHz, any width, to link A. Read response from link A to PCI-X, 133 MHz, any width.
Table 7: Some latencies.
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5 5.1
Registers Register Overview
The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers to register addresses that are accessed through x86 IO instructions such as IN and OUT. PCI configuration space is typically accessed by the host through IO cycles to CF8h and CFCh. There is also memory space and indexed address space in the IC.
5.1.1 Configuration Space
The address space for the IC configuration registers is broken up into busses, devices, functions, and, offsets, as defined by the link specification. It is accessed by HyperTransportTM technology-defined type 0 configuration cycles. The device number is mapped into bits[15:11] of the configuration address. The function number is mapped into bits[10:8] of the configuration address. The offset is mapped to bits[7:2] of the configuration address. The following diagram shows the devices in configuration space as viewed by software.
Primary bus IOAPIC DevA:1xXX Device header First device Function 1 PCIX Bridge DevA:0xXX Bridge header First device Function 0 PCIX Bridge DevB:0xXX Bridge header Second device Function 0 IOAPIC DevB:1xXX Device header Second device Function 1
External PCIX bus devices
External PCIX bus devices
Secondary bus
Secondary bus
Figure 12: Configuration space.
Device A, above, is programmed to be the link base UnitID and device B is the link base UnitID plus 1.
5.1.2 Register Naming and Description Conventions
Configuration register locations are referenced with mnemonics that take the form of Dev[A|B]:[7:0]x[FF:0], where the first set of brackets contain the device number, the second set of brackets contain the function number, and the last set of brackets contain the offset. Other register locations (e.g., memory mapped registers) are referenced with an assigned mnemonic that specifies the address space and offset. These mnemonics start with two or three characters that identify the space followed by characters that identify the offset within the space. Register fields within register locations are also identified with a name or bit group in brackets following the register location mnemonic.
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The following are configuration spaces:
Device "A" "A" "B" "B" Function 0 1 0 1 Mnemonic Registers DevA:0xXX PCI-PCI bridge A registers; link and PCI-X capabilities block DevA:1xXX IOAPIC for PCI-X bridge A. DevB:0xXX PCI-PCI bridge B registers; PCI-X capabilities block DevB:1xXX IOAPIC for PCI-X bridge B.
Table 8: Configuration spaces.
The IC does not claim configuration-register accesses to unimplemented functions within its devices (they are forwarded to the other side of the tunnel). Accesses to unimplemented register locations within implemented functions are claimed; such writes are ignored and reads always respond with all zeros. The following are memory mapped spaces:
Base address register Dev[B,A]:1x10/48 Dev[B,A]:0x10 Size (bytes) 4K 4K Mnemonic Registers IOAXX IOAPIC registers. Base address register at offset 10h enabled by Dev[B, A]:1x44[OSVISBAR].
SHPC[B,A]: Standard hot plug controller register set. Access to these registers is XX enabled by DevA:0x48[HPENB, HPENA]. Access to these registers is provided through both memory space and configuration space; to access through configuration space, Dev[B, A]:0x90[SELECT] specifies the DWORD offset and Dev[B, A]:0x94 provides the DWORD data port.
Table 9: Memory mapped address spaces.
The following are register attributes found in the register descriptions.
Type Read or read-only Write Set by hardware Write once Description Capable of being read by software. Read-only implies that the register cannot be written to by software. Capable of being written by software. Register bit is set high by hardware. After RESET#, these registers may be written to once. After being written, they become read only until the next RESET# assertion. The write-once control is byte based. So, for example, software may write each byte of a write-once DWORD as four individual transactions. As each byte is written, that byte becomes read only. Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no effect. Software can set the bit high by writing a 1 to it. However subsequent writes of 0 will have no effect. RESET# must be asserted in order to clear the bit.
Write 1 to clear Write 1 only
Table 10: Register attributes.
5.2 PCI-X Bridge Configuration Registers
These registers are located in PCI configuration space, in the first device (device A) and second device (device B), function 0. See section 5.1.2 for a description of the register naming convention.
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PCI-X Bridge Vendor And Device ID Register
Dev[B, A]:0x00
Default: 7450 1022h Bits Description 31:16 PCI bridge device ID. 15:0 Vendor ID.
Attribute: Read only.
PCI-X Bridge Status And Command Register
Dev[B, A]:0x04
Default: 0230 0000h Bits Description 31 30
Attribute: See below.
DPE: detected parity error. Read only. This bit is fixed in the low state. SSE: signaled system error. Read; set by hardware; write 1 to clear. 1=A system error was signaled (both links were flooded with sync packets). This bit cannot be set unless Dev[B, A]:0x04[SERREN] is high. Note: this bit is cleared by PWROK reset but not by RESET#. RMA: received master abort. Read; set by hardware; write 1 to clear. 1=A request sent to the host bus received a master abort (an NXA error response). Note: this bit is cleared by PWROK reset but not by RESET#. RTA: received target abort. Read; set by hardware; write 1 to clear. 1=A request sent to the host bus received a target abort (a non-NXA error response). Note: this bit is cleared by PWROK reset but not by RESET#. STA: Signaled target abort. Read; set by hardware; write 1 to clear. 1=A target abort was signaled to the host (a non-NXA error response). Note: this bit is cleared by PWROK reset but not by RESET#. Capabilities pointer. Read only. This bit is fixed in the high state. SERREN: SERR# enable. Read-write. 1=Dev[B, A]:0x04[SSE] is enabled to be set high in response to detected system errors. 0=Dev[B, A]:0x04[SSE] cannot be set high and the IC does not flood the links with sync packets.
29
28
27
26:21 Read only. These bits are fixed in their default state. 20 8 19:9 Reserved
7 6 5 4 3 2 1
Reserved.
PERSP: Parity error response. Read-write. This bit controls no hardware. It is provided for compatibility with the PCI-PCI bridge specification.
Reserved.
MWIEN: Memory write and invalidate enable. Read-write. This bit does not control any internal hardware; it is provided for compatibility with the PCI-PCI bridge specification. Special cycle enable. Read only. This bit is hardwired low. MASEN: PCI master enable. Read-write. 1=Enables secondary bus masters to initiate cycles to the host. MEMEN: memory enable. Read-write. 1=Enables access to the secondary bus memory space and to the SHPC register space through the memory-space BAR, Dev[B, A]:0x10 (this bit does not affect access to SHPC registers through configuration space, Dev[B, A]:0x[94:90]). IOEN: IO enable. Read-write. 1=Enables access to the secondary bus IO space.
0
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PCI-X Bridge Revision and Class Code Register
Dev[B, A]:0x08
Default: 0604 0?11h Bits Description
Attribute: Read only.
31:8 CLASSCODE. Provides the bridge class code as defined in the PCI specification. Bits[3:1] of this register are zero. DevA:0x08[8] is the same as DevA:0x48[COMPAT]. DevB:0x08[8] is zero. 7:0
REVISION.
PCI-X Bridge BIST-Header-Latency-Cache Register
Dev[B, A]:0x0C
Default: 0081 ??00h Bits Description
Attribute: See below.
31:24 BIST. Read only. These bits are fixed at their default values. 23:16 HEADER. Read only. These bits are fixed at their default values. 15:8 LATENCY. Read-write. These bits control no hardware. The default value after the deassertion of RESET# is 00h when the bridge is in conventional PCI mode and 40h when the bridge is in PCI-X mode. 7:0
CACHE. Read only. These bits are fixed at their default values.
PCI-X SHPC Base Address Register
Dev[B, A]:0x10
This register is reserved if DevA:0x48[HPENB, HPENA] is low. Default: 0000 0000 0000 0004h Bits Description Attribute: See below.
63:12 SHPCBAR: SHPC base address register. Read-write. These bits specify the memory address space of the SHPC register set, SHPC[B, A]:xx. Note: bits[63:40] are required to be programmed low; setting any of these bits high results in undefined behavior. 11:0 Hardwired. Read only. These bits are all hardwired to their default state to indicate a 4K byte block of 64-bit, non-prefetchable memory space.
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PCI-X Bridge Bus Numbers And Secondary Latency Register
Dev[B, A]:0x18
Default: ??00 0000h Bits Description
Attribute: See below.
31:27 SECLAT[7:3]. Read-write. Secondary latency timer. The default value of SECLAT[7:0] after the deassertion of RESET# is 00h when the bridge is in conventional PCI mode and 40h when the bridge is in PCI-X mode. 26:24 SECLAT[2:0]. Read only, 000b. Secondary latency timer. 23:16 SUBBUS. Read-write. Subordinate bus number. 15:8 SECBUS. Read-write. Secondary bus number. 7:0
PRIBUS. Read-write. Primary bus number.
PCI-X Bridge Memory Base-Limit Registers
Dev[B, A]:0x[30:1C]
These registers specify the IO-space (Dev[B, A]:0x1C and Dev[B, A]:0x30), non-prefetchable memory-space (Dev[B, A]:0x20), and prefetchable memory-space (Dev[B, A]:0x24, Dev[B, A]:0x28, and Dev[B, A]:0x2C) address windows for transactions that are mapped from the 40-bit link address space to the secondary PCI bus. The links support 25 bits of IO space. PCI-X supports 32 bits of IO space. Host accesses to the link-defined IO region are mapped to the PCI-X IO window with the 7 MSB always zero. PCI-X IO accesses in which any of the 7 MSBs are other than zero are ignored. The PCI-X IO space window is defined as follows:
PCI-X IO window = {7'h00, Dev[B,A]:30[24:16], Dev[B,A]:0x1C[15:12], 12'hFFF} >= address >= {7'h00, Dev[B,A]:30[8:0], Dev[B,A]:0x1C[7:4], 12'h000};
The links and PCI-X support 40 bits of memory space. The PCI-X non-prefetchable memory space window is defined as follows:
PCI-X non-prefetchable memory window = {24'h00, DevA:0xD8[15:8], Dev[B,A]:0x20[31:20], 20'hF_FFFF} >= address >= {24'h00, DevA:0xD8[7:0], Dev[B,A]:0x20[15:4], 20'h0_0000};
The links support 40 bits of memory space. PCI-X supports 64 bits of prefetchable memory space. All link memory mapped IO space may be within the PCI-X prefetchable memory window. PCI-X memory accesses in which any of bits[63:40] are other than zero are ignored. The PCI-X prefetchable memory space window is defined as follows:
PCI-X prefetchable memory window = {24'h0, Dev[B,A]:2C[7:0], Dev[B,A]:0x24[31:20], 20'hF_FFFF} >= address >= {24'h0, Dev[B,A]:28[7:0], Dev[B,A]:0x24[15:4], 20'h0_0000};
These windows may also be altered by Dev[B, A]:0x3C[VGAEN, ISAEN]. When the address (from either the host or from a secondary bus master) is inside one of the windows, then the transaction is assumed to be intended for a target that sits on the secondary bus. Therefore, the following transactions are possible: * Host-initiated transactions inside the windows are routed to the secondary bus. * Secondary PCI-initiated transactions inside the windows are not claimed by the IC.
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* Host initiated transactions outside the windows are passed through the tunnel or master aborted if the IC is at the end of a chain. * Secondary PCI-initiated transactions outside the windows are claimed by the IC using medium decoding and passed to the host. So, for example, if IOBASE > IOLIM, then no host-initiated IO-space transactions are forwarded to the secondary bus and all secondary-PCI-bus-initiated IO-space (not configuration) transactions are forwarded to the host. If MEMBASE > MEMLIM and PMEMBASE > PMEMLIM, then no host-initiated memory-space transactions are forwarded to the secondary bus and all secondary-PCI-bus-initiated memory-space transactions are forwarded to the host. The window may be affected by DevA:0x48[COMPAT] as well.
Dev[B, A]:0x1C. Default: 0220 01F1h Bits Description
Attribute: See below.
31
DPE: detected parity error. Read; set by hardware; write 1 to clear. 1=The IC detected an address parity error as the target of a secondary bus cycle or a data parity error during a data phase of an upstream transaction. RSE: received system error. Read; set by hardware; write 1 to clear. 1=The IC detected that either [B, A]_SERR# or [B, A]_SHPC_SERR is asserted. In order to clear this bit, these signals must be deasserted. Note: this bit is cleared by PWROK reset but not by RESET#. RMA: received master abort. Read; set by hardware; write 1 to clear. 1=The IC received a master abort as a master on the secondary bus. Note: this bit is cleared by PWROK reset but not by RESET#. RTA: received target abort. Read; set by hardware; write 1 to clear. 1=The IC received a target abort as a master on the secondary PCI bus. Note: this bit is cleared by PWROK reset but not by RESET#. STA: signaled target abort. Read; set by hardware; write 1 to clear. 1=The IC generated a target abort as a target on the secondary PCI bus. Note: this bit is cleared by PWROK reset but not by RESET#. MDPE: master data parity error. Read; set by hardware; write 1 to clear. 1=The IC detected a parity error during a data phase of a read or detected [B, A]_PERR# asserted during a write as a master on the secondary bus and Dev[B, A]:0x3C[PEREN] is set. FBBEN: fast back to back enable. Read only. This bit is fix in the low state to indicate that the IC does not support fast back to back transactions from different masters.
30
29 28
27
26:25 Device select timing. Read only. These bits are hard wired to indicate medium decoding. 24
23
22:16 Read only. These bits are fixed in their default state. 15:12 IOLIM. IO limit address bits[15:12]. See Dev[B, A]:0x[30:1C] above. 11:8 Reserved. 7:4 3:0
IOBASE. IO base address bits[15:12]. See Dev[B, A]:0x[30:1C] above.
Reserved.
Dev[B, A]:0x20. Default: 0000 FFF0h Bits Description
Attribute: Read-write.
31:20 MEMLIM. Non-prefetchable memory limit address bits[31:20]. See Dev[B, A]:0x[30:1C] above.
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19:16 Reserved. 15:4 MEMBASE. Non-prefetchable memory base address bits[31:20]. See Dev[B, A]:0x[30:1C] above. 3:0 Reserved.
Dev[B, A]:0x24. Default: 0001 FFF1h Bits Description
Attribute: Read-write.
31:20 PMEMLIM. Prefetchable memory limit address bits[31:20]. See Dev[B, A]:0x[30:1C] above. 19:16 Reserved. 15:4 PMEMBASE. Prefetchable memory base address bits[31:20]. See Dev[B, A]:0x[30:1C] above. 3:0
Reserved.
Dev[B, A]:0x28. Default: 0000 0000h Bits Description
Attribute: Read-write.
31:0 PMEMBASE. Prefetchable memory base address bits[63:32]. See Dev[B, A]:0x[30:1C] above.
Dev[B, A]:0x2C. Default: 0000 0000h Bits Description
Attribute: Read-write.
31:0 PMEMLIM. Prefetchable memory limit address bits[63:32]. See Dev[B, A]:0x[30:1C] above.
Dev[B, A]:0x30. Default: 0000 FFFFh Bits Description
Attribute: Read-write.
31:16 IOLIM. IO limit address bits[31:16]. See Dev[B, A]:0x[30:1C] above. 15:0 IOBASE. IO base address bits[31:16]. See Dev[B, A]:0x[30:1C] above.
PCI-X Bridge Capabilities Pointer Register
Dev[B, A]:0x34
Default: 0000 00A0h Bits Description 31:8 Reserved. 7:0
Attribute: Read only.
CAPABILITIES_PTR. Specifies the offset to standard PCI-X registers.
PCI-X Bridge Interrupt and Bridge Control Register
Dev[B, A]:0x3C
Default: 0000 0?FFh Bits Description 31:28 Reserved.
Attribute: See below.
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27
DTSE: discard timer sync flood enable. Read-write. 1=If both Dev[B, A]:0x04[SERREN] and Dev[B, A]:0x3C[DTS] are high, then Dev[B, A]:0x04[SSE] is set and the links are flooded with sync packets. DTS: discard timer status. Read; set by hardware; write 1 to clear. 1=The 15-bit discard timer timed out. This bit is not capable of being set when the secondary bus is in PCI-X mode. Note: this bit is cleared by PWROK reset but not by RESET#. SBRST: secondary bus reset. Read-write. 1=[B, A]_PRESET# asserted; secondary PCI bus placed into reset state. 0=[B, A]_PRESET# not asserted. Note: the PCI requirement for a delay between the rising
edge of RST# and the first configuration access is not enforced by the IC with hardware; it is expected that this requirement be enforced through software.
26
25:23 Reserved. 22
21
MARSP: master abort response. Read-write. 1=The response to non-posted requests that come from the host bus or secondary bus that results in a master aborts will indicate a target abort to the initiating bus (through PCI bus protocol or link protocol); posted requests that are master aborted result in assertion of Dev[B, A]:0x04[SSE]. 0=Master aborts result in normal responses; read responses are sent with the appropriate amount of data, which are all 1s, and writes are ignored.
20 19
Reserved.
VGAEN: VGA decoding enable. Read-write. 1=Route host-initiated commands targeting VGAcompatible address ranges to the secondary bus. These include memory accesses from A0000h to BFFFFh (within the bottom megabyte of memory space only), IO accesses in which address bits[9:0] range from 3B0h to 3BBh or 3C0h to 3DFh (address bits[15:10] are not decoded, regardless of Dev[B, A]:0x3C[ISAEN]; also this only applies to the first 64K of IO space; i.e., address bits[31:16] must be low). 0=The IC does not decode VGA-compatible address ranges. ISAEN: ISA decoding enable. Read-write. 1=The IO address window specified by Dev[B, A]:0x1C[15:0] and Dev[B, A]:0x30 is limited to the first 256 bytes of each 1K byte block specified; this only applies to the first 64K bytes of IO space. 0=The PCI IO window is the whole range specified by Dev[B, A]:0x1C[15:0] and Dev[B, A]:0x30. SERREN: system error enable. Read-write. If Dev[B, A]:0x04[SERREN] and Dev[B, A]:0x3C[SERREN] are both high and if [B, A]_SERR# or [B, A]_SHPC_SERR is detected asserted (Dev[B, A]:0x1C[RSE] = 1), then the IC responds by flooding the outgoing link with sync packets and sets Dev[B, A]:0x04[SSE]. If either Dev[B, A]:0x04[SERREN] or Dev[B, A]:0x3C[SERREN] are low, then Dev[B, A]:0x1C[RSE] does not stop link operation or cause Dev[B, A]:0x04[SSE] to be set. PEREN: parity error response enable. Read-write. 1=Enable parity error detection on secondary PCI interface (see Dev[B, A]:0x1C[MDPE]); [B, A]_PERR# signal enabled to set status bit or be driven. 0=Dev[B, A]:0x1C[MDPE] cannot be set; [B, A]_PERR# signal is ignored and it is not driven by the IC.
18
17
16
15:8 INTERRUPT_PIN. Read only. If DevA:0x48[HPENB, HPENA] is low, then Dev[B, A]:0x3C[INTERRUPT_PIN] is 00h. If DevA:0x48[HPENB, HPENA] is high, then Dev[B, A]:0x3C[INTERRUPT_PIN] is 01h. When hot plug mode is enabled, [B, A]_PIRQA# can be asserted for hot plug events. 7:0
INTERRUPT_LINE. Read-write. These bits control no internal logic.
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PCI-X Miscellaneous Register
Dev[B, A]:0x40
Default: 001F 0001h. Bits Description
Attribute: See below.
31:28 PCLKDEL: [B, A]_PCLK[4:0] delay. Read-write. Relative to [B, A]_PLLCLKO, [B, A]_PCLK[4:0] are delayed by PCLKDEL*TAP_DELAY, where TAP_DELAY is defined by DevA:0x48[BDCV]. When a new value is written to this field, there may be a glitch on the output clocks. If [B, A]_PCLK[4:0] are used as the reference clock to PLLs external to the IC, then changing this field may cause these PLLs to lose synchronization. For this reason, it is recommended that [B, A]_PRESET# be asserted (through Dev[B, A]:0x3C[SBRST]) while this field is updated and that [B, A]_PRESET# be deasserted at least 1 millisecond after this field is updated. See section 4.3 for more information about [B, A]_PCLK[4:0]. 27:24 PLLODEL: PLLCLKO delay. Read-write. Relative to [B, A]_PCLK[4:0], [B, A]_PLLCLKO is delayed by PLLODEL*TAP_DELAY, where TAP_DELAY is defined by DevA:0x48[BDCV]. When a new value is written to this field, the clock delay is shifted such that there is no glitch on the output signal. Changing this field may cause the internal PLL that generates [B, A]_PCLK[4:0] to lose synchronization for a period of no more than 100 microseconds. For this reason, it is recommended that software alter this value by only one at a time. E.g., to change from 0 to 3, software should write a 1, then write a 2, then write a 3 to this field. See section 4.3 for more information about [B, A]_PLLCLKO. 23:21 Reserved. 20:16 PCLKEN: PCLK enable. Read-write. Each of these bits controls a [B, A]_PCLK[4:0] signal. Bit 16 controls PCLK 0, bit 17 controls PCLK1, and so forth. 1=The PCLK signal is enabled to toggle. 0=The PCLK signal is forced low. It is intended that this be used to disable PCLK signals that correspond to unimplemented PCI-X devices or slots. 15:13 Reserved. 12:8 PFEN[4:0]#: prefetch enables (active low). Read-write. Each of these bits apply to one [B, A]_REQ#/GNT# pair (Dev[B, A]:0x40[PFEN0#] applies to [B, A]_REQ0#/GNT0# and so forth). 0=Prefetching is enabled for the specified external master in conventional PCI mode. 1=Prefetching is not enabled. When prefetching is not enabled, memory read requests from external masters are allowed to burst from the transaction starting address up to the 64-byte cacheline boundary, at which point the transaction is disconnected with data. If prefetching is enabled, while the burst is taking place, the next cacheline is read from the host such that the burst may be continued for multiple cachelines. This field is ignored when the bridge is in PCI-X mode (Dev[B, A]:0xA0[SCF] is not zero). It is expected that these bits are normally left at 0. 7:5 4 Reserved.
NZSEQID: non-zero sequence ID. Read-write. 0=The SeqID value is 0h in the upstream link requests that result from the bridge's PCI master memory read requests. 1=The SeqID value is not zero in the upstream link requests that result from the bridge's PCI master memory read requests; if DevA:0x40[NZSEQID] is high, then a SeqID of 1h is generated for these transactions from bridge A; if DevB:0x40[NZSEQID] is high, then a SeqID of 2h is generated for these transactions from bridge B. This applies only to memory read requests from external masters. Setting these bits high may reduce host memory efficiency and bandwidth. It is not expected that these bits will need to be set; the order in which requests are delivered to destinations does not matter in most cases. Must be low. Read-write. This bit is required to be low at all times; setting it high results in undefined behavior.
3
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2
HPSSS#: hot plug single-slot support (active low). Read only. The default state of DevA:0x40[HPSSS#] is captured off of HPSIC at the rising edge of PWROK. The default state of DevB:0x40[HPSSS#] is captured off of B_GNT2# at the rising edge of PWROK. 0=If the bridge is in hot plug mode (as specified by DevA:0x48[HPENB or HPENA]), then the bridge supports a single hot plug slot without external isolation switches. In this mode, external isolation switches between the IC and the slot are not required. See section 4.5.3 for details. 1=External isolation switches are required for all hot plug slots. This bit is required to be high if more than one external device is supported by the bridge. If HPSSS# is low while the DevA:0x48[HPENB, HPENA] bit corresponding to the same bridge is low, then undefined behavior results. CPCI66: conventional PCI mode frequency. Read only. Dev[B, A]:0xA0[SCF]=0h, then the bridge is in conventional PCI mode and this bit is valid; otherwise its state is unknown. 0=[B, A]_PCLK[4:0] toggle at 33 MHz. 1=[B, A]_PCLK[4:0] toggle at 66 MHz. The default state for this field is determined by strapping options described in section 4.2. NIOAMODE: non-IOAPIC mode. Read-write. This is used to enable [B, A]_PIRQ[D, C, B, A]# to the NIOAIRQ[D, C, B, A]# pins. 0=The state of the PIRQ[D:A]# pin is passed to the NIOAIRQ[D:A]# pin as if the PIRQ[D:A]# pin were always high. 1=The state of the PIRQ[D:A]# pin from the bridge is ANDed with the state from the other bridge and passed to the NIOAIRQ[D:A]# pin. This is shown in the following equations:
NIOAIRQA# = ~( | NIOAIRQB# = ~( | DevA:0x40[NIOAMODE] DevB:0x40[NIOAMODE] DevA:0x40[NIOAMODE] DevB:0x40[NIOAMODE] & & & & ~A_PIRQA# ~B_PIRQA# ~A_PIRQB# ~B_PIRQB# & & & & RDRA0[IM] RDRB0[IM] ); RDRA1[IM] RDRB1[IM] );
1
0
And similarly for NIOAIRQ[C and D]#. Were RDR[B, A][3:0][IM] is the interrupt mask field of the redirection register (see section 5.4); [B, A] = the bridge letter; [3:0] = the redirection register index. Note that the NIOAIRQ[D:A]# pins are open drain outputs. So a high on the PIRQ input is translated to the high-inpedence state on the NIOAIRQ output. See section 4.5.2 for more details about interrupt routing. It is expected that this bit is normally left high by system BIOS.
PCI-X Miscellaneous II Register
Dev[B, A]:0x44
Default: 0000 0000h. Bits Description
Attribute: Read-write.
31:1 RW. Read-write. These bits control no hardware. These bits are reserved and should be left in the default state. 0
NMIEN: NMI on error enable. Read-write. 1=Assertions of the [B, A]_PERR# and [B, A]_SERR# signals (regardless of the source of the assertion) result in NMI interrupts; see section 4.5.2.1.
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Pins Latched At Boot Register
DevA:0x48
The default value for bits in this register is latched at the rising edge of PWROK. Default: 0000 000?h. Bits Description 31:12 Reserved. 11:8 BDCV: buffer delay calculation value. Read only. This provides the approximate buffer delay calculation value used to determine the delay value of each tap in Dev[B, A]:0x40[PLLODEL and PCLKDEL] as follows: TAP_DELAY ~= 1250/BDCV picoseconds. Expected values for BDCV are from 5h to Fh. 7:4 3 Reserved.
HPENB: bridge B hot plug enable. Read only. This bit captures the state of HPSIL# at the rising edge of PWROK. 0=Hot plug mode is not enabled on bridge B. 1=Hot plug mode is enabled on bridge B. See section 4.5.3 for details. If this bit is low while DevB:0x40[HPSSS#] is low, then undefined behavior results. HPENA: bridge A hot plug enable. Read only. This bit captures the state of HPSOD at the rising edge of PWROK. 0=Hot plug mode is not enabled on bridge A. 1=Hot plug mode is enabled on bridge A. See section 4.5.3 for details. If this bit is low while DevA:0x40[HPSSS#] is low, then undefined behavior results.
Attribute: See below.
2
1 0
Reserved.
COMPAT: compatibility bus. Read-write. 1=The IC routes all host initiated accesses in which the link-defined compat bit is set to the secondary bus. The default state of this bit is latched off of A_COMPAT at the trailing edge of PWROK reset.
Prefetch Control Register
Dev[B, A]:0x4C
This register specifies the prefetching policy when a bridge is in conventional PCI mode. This register is ignored when in PCI-X mode. It includes three sets of initial prefetch registers (IPF_x) and three corresponding sets of continuous prefetch enable registers (CPFEN_x): one for memory read multiple requests (x=MRM); one for memory read line requests (x=MRL); and one for memory read requests (x=MR). When a PCI master, for which prefetching is enabled through Dev[B, A]:0x40[PFEN#], initiates a host read with a command code of MRM, MRL, or MR, then the IC sends link read requests as follows: (1) an initial up-to-one cacheline request from the initial address to the end of the cacheline and (2) additional cachelines as specified by the IPF_x field that corresponds to the command code issued by the PCI master. When each cacheline of data starts to be transferred to the master over the PCI bus, an additional cacheline of data may be requested, as specified by the appropriate CPFEN_x bit. An unrequested prefetch, as specified in some of the fields of this register, is a speculative link request--or prefetch--generated by the IC for a cacheline of data beyond the cacheline address generated by the conventional PCI master; a requested prefetch is up-to-one cacheline of memory read data at an address generated by the conventional PCI master. See section 4.6.1 for information about how prefetching is related to performance. Default: 0000 2C00h. Bits Description 31:14 Reserved. Attribute: Read-write.
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13
CPFEN_MRM. Continuous prefetch enable for memory read multiple request. When a master initiates a burst read to the host with a memory read multiple command code, this specifies if continuous prefetching is enabled. 1 = One new request for a cacheline of prefetch data is sent to the host by the IC when data from an earlier cacheline starts to be transferred to the requesting master over the PCI bus. 0 = There are no new requests for prefetch data after the initial batch specified by IPF_MRM.
12:10 IPF_MRM: Initial prefetch for memory read multiple request. This specifies the number of additional cacheline prefetches (after the initial prefetch of up to one cacheline) when a PCI master initiates a burst read to the host with a memory read multiple command code. If prefetching is disabled in Dev[B, A]:0x40[PFEN#], then the value of this register is ignored. 0=no additional prefetches; 1=1 additional prefetch; 2=2 additional prefetches, and so forth. 9 8:6 5 4:2 1
CPFEN_MRL. Continuous prefetch enable for memory read line request. See CPFEN_MRM. IPF_MRL: Initial prefetch for memory read line request. See IPF_MRM. CPFEN_MR. Continuous prefetch enable for memory read request. See CPFEN_MRM. IPF_MR: Initial prefetch for memory read request. See IPF_MRM. DPDM: Discard unrequested prefetch data upon master request. 1=No further prefetching occurs and all unrequested prefetches are discarded when another master requests the PCI bus; also, unrequested prefetches are discarded if the discard timer reaches 16 PCLKs (requested prefetches are discarded if the discard timer reaches 32K PCLKs). 0=Requests from other masters do not affect prefetching; requested and unrequested prefetches are discarded if the discard timer reaches 32K PCLKs. This bit is typically programmed low by system BIOS. DPDH: Discard unrequested prefetch data upon host request. 1=If the IC receives a host request to the PCI bus, then: (1) if there is not an outstanding requested prefetch for a given previously-established PCI read request, then all of the unrequested prefetches associated with that PCI read request are discarded; or (2) if there is an outstanding requested prefetch for a given previously-established PCI read request, then the data for that requested prefetch, along with the data for subsequent unrequested prefetches, is allowed to burst onto the PCI bus until the burst is disconnected (either by the PCI master or by the IC because it does not possess the data necessary to continue the burst); when the burst is disconnected, any remaining unrequested prefetches associated with the PCI read request are discarded. (3) if there is a burst in progress on the PCI bus, the IC disconnects the burst at the next convenient cacheline boundary and discards any outstanding unrequested prefetches associated with the transaction. 0=Host requests do not affect prefetching.
0
Programming of this bit may vary based on platform requirements. DPDH is typically programmed high by system BIOS to protect against stale prefetch-data scenarios, as described in the PCI specification, revision 2.3, section 3.10, point 6; scenarios similar to this have been observed, albeit rarely. However, if the secondary PCI bus includes a device that is accessed frequently as a target, then setting this bit may result in reduced memory read bandwidth. In such cases, it may be preferable to program this bit low.
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AMD-8131TM PCI-X Tunnel Data Sheet
PCI-X PHY Compensation Control Registers
DevA:0x[54, 50]
The PCI-X PHY circuitry includes automatic compensation that is used to adjust the drive strength of the PCIX and other IO cells, including all output signals of the IC that are on the VDD33 power plane. The compensation circuits calculate the drive strength for the rising edge and falling edge of the outputs. These registers provide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a fixed difference. The overrides and difference values may be different between bridges A and B. These registers specify the compensation parameters as follows: * DevA:0x50: output rising edge (P) drive strength compensation; associated with the P_CAL pin. * DevA:0x54: output falling edge (N) drive strength compensation; associated with the P_CAL# pin. Higher values in these registers represent higher drive strength; the values range from 0h to Fh (16 steps). Default: 0000 0000. Bits Description 31 Attribute: See below.
Must be low. Read-write. This bit is required to be low at all times; setting it high results in undefined behavior.
30:20 Reserved. 19:16 CALCCOMP: calculated compensation value. Read only. This provides the calculated value from the auto compensation circuitry. The default value of this field is not predictable. DevA:0x50[CALCCOMP] is affected by the value of the resistor connected to P_CAL and DevA:0x54[CALCCOMP] is affected by the value of the resistor connected to P_CAL#. In both cases, larger the values of resistors (measured in ohms) result in smaller CALCCOMP values. 15 Reserved. 14:13 BCTL: Bridge B PHY control value. Read-write. These two bits combine to specify the PHY compensation value that is applied to bridge B outputs as follows: BCTL 00b 01b 10b 11b Description Apply CALCCOMP directly as the compensation value. Apply BDATA directly as the compensation value. Apply the sum of CALCCOMP and BDATA as the compensation value. If the sum exceeds Fh, then Fh is applied. Apply the difference of CALCCOMP minus BDATA as the compensation value. If the difference is less than 0h, then 0h is applied.
12
Reserved.
11:8 BDATA: Bridge B data value. Read-write. This value is appled to the bridge B PHY compensation as described in BCTL. 7 Reserved.
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6:5
ACTL: Bridge A PHY control value. Read-write. These two bits combine to specify the PHY compensation value that is applied to bridge A outputs as follows:
ACTL 00b 01b 10b 11b
Description Apply CALCCOMP directly as the compensation value. Apply ADATA directly as the compensation value. Apply the sum of CALCCOMP and ADATA as the compensation value. If the sum exceeds Fh, then Fh is applied. Apply the difference of CALCCOMP minus ADATA as the compensation value. If the difference is less than 0h, then 0h is applied.
4 3:0
Reserved
ADATA: Bridge A data value. Read-write. This value is appled to the bridge A PHY compensation as described in ACTL.
SHPC Capabilities Register
Dev[B, A]:0x90
This register is reserved if DevA:0x48[HPENB, HPENA] is low. Default: 0000 980Ch Bits Description 31 30 Attribute: See below.
CIP: Controller Interrupt Pending. Read only. 1=One or more bits in SHPC[B, A]:18 is set. 0=All bits in SHPC[B, A]:18 are cleared. CSERRP: Controller System Error Pending. Read only. 1=One or more bits in SHPC[B, A]:1C is set. 0=All bits in SHPC[B, A]:1C are cleared.
29:24 Reserved. 23:16 SELECT: DWORD Select. Read-write. Specifies the DWORD from the SHPC[B, A]:XX register set that is accessible through Dev[B, A]:0x94. 00h selects SHPC[B, A]:00; 01h selects SHPC[B, A]:04; and so on. 15:8 Next Capability Pointer. Read only. Points to the next capability block. 7:0
Capabilities ID. Read only. Specifies the capabilities ID for SHPC.
SHPC Data Register
Dev[B, A]:0x94
This register is reserved if DevA:0x48[HPENB, HPENA] is low. Default: 0000 0000h Bits Description Attribute: Read-write.
31:0 DATA: SHPC data port. Accesses to this port access the register of the SHPC[B, A]:XX register set that is indexed by Dev[B, A]:0x90[SELECT].
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Power Management Capabilities Register
Dev[B, A]:0x98
This register is reserved if DevA:0x48[HPENB, HPENA] is low. Default: 480A ??01h Bits Description Attribute: Read only.
31:27 PMES: PME support. Indicates PME# support in device state D0 (system state S0) and device state D3 hot (system state S1). 26 25
D2S: D2 support. Indicates that D2 device power state is not supported. D1S: D1 support. Indicates that D1 device power state is not supported.
24:22 AUXCR: auxiliary current requirements. Indicates that there is no requirement for auxiliary current since the D3 cold device power state is not supported. 21 20 19
DSI: Device specific initialization. Indicates that there is no special initialization requirement.
Reserved.
PMECLK: PME clock. Indicates that the PCI clock is required for PME# generation.
18:16 Version. Specifies that the PCI function complies with Revision 1.1 of the PCI Power Management Interface Specification. 15:8 Next Capability Pointer. Read only. Points to the next capability block. DevA:0x98[15:8]=C0h. DevB:0x98[15:8]=00h. 7:0
Capabilities ID. Specifies the Capabilities ID for PCI Power Managament.
Power Management Status and Control Register
Dev[B, A]:0x9C
This register is reserved if DevA:0x48[HPENB, HPENA] is low. Default: 0000 0000h Bits Description 31:24 Reserved. 23
BPCC_EN: bus power/clock control enable. Read only. Indicates that the bus power/clock control policies defined in Section 4.7.1 of the PCI Bus Power Management Interface Specification Rev. 1.1 have been disabled. PME_STS: PME# status. Read; set by hardware; write 1 to clear. Set when [B, A]_PME# is asserted as a result of an SHPC PME event (see SHPC[B, A]:20). PME_EN: PME enable. Read-write. 1=Enables [B, A]_PME# assertion if Dev[B, A]:0x9C[PME_STS] is set.
Attribute: See below
22:16 Reserved. 15
14:9 Reserved. 8 7:2 1:0
Reserved.
PWRS: power state. Read-write. Indicates the current power state of the function. 00b = D0. 11b = D3 hot. If software attempts to write unsupported state to this field (01b = D1 or 10b = D2), the write operation completes normally on the bus; however, the data is discarded and no state change occurs.
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AMD-8131TM PCI-X Tunnel Data Sheet
PCI-X Secondary Status Register
Dev[B, A]:0xA0
Default: 0??3 B807h (bits[21:20] reset to low; see below for bits[24:22]).Attribute: See below. Bits Description 31:25 Reserved. 24:22 SCF: secondary clock frequency. Read only. This specifies the frequency of the secondary bus the last time [B, A]_PRESET# was asserted. 0h=conventional PCI mode; 1h=66 MHz PCI-X mode; 2h=100 MHz PCI-X mode; 3h=133 MHz PCI-X mode; 4h-7h are reserved. The default state for this field is determined by strapping options described in section 4.2. 21
SRD: split request delayed. Read only; hardwired low. The IC automatically limits the number of upstream link read requests to the number of downstream buffers available; so there is no reason to limit the number of ADQs in read requests accepted by the IC. SCO: split completion overrun. Read only; hardwired low. The IC automatically limits the number of downstream PCI-X read requests to the number of upstream response buffers available; so there is no reason to terminate a split completion for this reason. USC: unexpected split completion. Read; set by hardware; write 1 to clear. 1=An unexpected Split Completion with a Requester ID equal to the bridge's secondary bus number, device number 00h, and function number 0 was received on the secondary interface. SCD: split completion discarded. Read; set by hardware; write 1 to clear. 1=The bridge discarded a split completion moving toward the secondary bus because the requester would not accept it. 133 MHz capable. Read only. This bit is hardwired high to indicate support for 133 MHz. 64-bit device. Read only. This bit is hardwired high to indicate a 64-bit secondary bus. Capabilities ID. Read only. Specifies the capabilities ID for PCI-X configuration space.
20
19
18 17 16 7:0
15:8 Next capability pointer. Read only. Points to the next capability block.
PCI-X Bridge Status Register
Dev[B, A]:0xA4
Default: 0003 0000h Bits Description 31:22 Reserved. 21
Attribute: See below.
SRD: split request delayed. Read only; hardwired low. The IC automatically limits the number of downstream PCI-X read requests to the number of upstream buffers available; so there is no reason to limit the number of ADQs in read requests accepted by the IC. Split completion overrun. Read only. This bit is hardwired low. Unexpected split completion. Read only. This bit is hardwired low. Split completion discarded. Read only. This bit is hardwired low. 133 MHz capable. This bit is set high arbitrarily. It has no meaning since the primary bus is not PCIX. 64-bit device. Read only. This bit is set high arbitrarily. It has no meaning since the primary bus is not PCI-X.
20 19 18 17 16
15:8 Bus number. Read only. These bits reflect the state of Dev[B, A]:0x18[PRIBUS].
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7:3 2:0
Device number. Read only. For DevA, these bits reflect the state of DevA:0xC0[BUID]. Fore DevB, these bits reflect the state of DevA:0xC0[BUID] plus 1. Function number. Read only. This is 0h to reflect the value of this function.
PCI-X Upstream Split Transaction Register
Dev[B, A]:0xA8
Default: FFFF 000Eh Bits Description
Attribute: See below.
31:16 USTCL: upstream split transaction commitment limit. Read-write. This register controls no hardware. The IC automatically limits the number of upstream link read requests to the number of downstream buffers available; so there is no reason to limit the number of ADQs in read requests accepted by the IC. This field is required to be greater than or equal to Dev[B, A]:0xA8[USTC]. A value of FFFFh specifies that there is no limit. It is expected that this register will be left at its default value by software. 15:0 USTC: upstream split transaction capacity. Read only. This field specifies the number of downstream response ADQs that can be stored for completion on the secondary bus.
PCI-X Downstream Split Transaction Register
Dev[B, A]:0xAC
Default: FFFF 0002h Bits Description
Attribute: See below.
31:16 DSTCL: downstream split transaction commitment limit. Read-write. This register controls no hardware. The IC automatically limits the number of downstream PCI-X read requests to the number of upstream buffers available; so there is no reason to limit the number of ADQs in read requests generated by the IC. This field is required to be greater than or equal to Dev[B, A]:0xAC[DSTC]. A value of FFFFh specifies that there is no limit. It is expected that this register will be left at its default value by software. 15:0 DSTC: downstream split transaction capacity. Read only. This field specifies the number of upstream response ADQs that can be stored for completion to the link.
Interrupt Discovery Configuration Registers
Dev[B, A]:0x[BC, B8]
These two locations duplicate access to the IOAPIC register space defined in section 5.4. Dev[B, A]:0xB8[INDEX] provides the index and Dev[B, A]:0xBC provides the data port. The definition of the indexed registers is as described in section 5.4. Some fields of the IDRDR register are identical to RDR fields (IM, POL, TM, DM, DEST, IRR); these represent duplicate access to the same physical registers (not duplicate registers). Other IDRDR fields (INTRINFO, PASSPW) represent new functionality. See section 4.5.2 for more information about interrupts.
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Dev[B, A]:0xB8. Default: 8000 ??08h Bits Description
Attribute: See below.
31:24 Capability type. Read only. This field is hardwired to indicate the link-defined interrupt discovery and configuration block. 23:16 INDEX. Read-write. Specifies the register accessed through the Dev[B, A]:0xBC dataport. This is the same as IOA00 described in section 5.4. 15:8 Next capability pointer. Read only. Points to the next capability block. The value of this register varies as follows: * If DevA:0x48[HPENA]=0 then DevA:0xB8[18:5]=C0h (HT capability block). * If DevA:0x48[HPENA]=1 then DevA:0xB8[18:5]=90h (hot plug capability block). * If DevA:0x48[HPENB]=0 then DevB:0xB8[18:5]=00h (last capability block). * If DevA:0x48[HPENB]=1 then DevB:0xB8[18:5]=90h (hot plug capability block). 7:0
Capabilities ID. Read only. Specifies the capabilities ID for link configuration space.
IDRDR. Default: 0000 0000 F800 0001h Bits Description
Attribute: See below.
63
IRR. Read; set by hardware; cleared by hardware or write 1 to clear. This provides duplicate access to RDR[IRR] described in section 5.4. However, writing a 1 to this bit clears this register; this is not the case with RDR[IRR]. PASSPW. Read-write. The state of this bit is reflected in the PassPW bit of the link interrupt request packet. It is expected to be programmed low in all cases.
62
61:56 Reserved. 55:24 INTRINFO[55:24]. Read-write. IntrInfo[55:24] in the link interrupt request packet. 23:16 IV. Read-write. IntrInfo[23:16] in the link interrupt request packet. This provides duplicate access to RDR[IV] described in section 5.4. 15:8 DEST. Read-write. IntrInfo[15:8] in the link interrupt request packet. This provides duplicate access to RDR[DEST] described in section 5.4. 7 6 5 4:2 1 0
INTRINFO[7]. Read-write. IntrInfo[7] in the link interrupt request packet. DM. Read-write. IntrInfo[6] in the link interrupt request packet. This provides duplicate access to RDR[DM] described in section 5.4. TM. Read-write. IntrInfo[5] in the link interrupt request packet. This provides duplicate access to RDR[TM] described in section 5.4. MT. Read-write. IntrInfo[4:2] in the link interrupt request packet. Accesses to RDR[MT] described in section 5.4. result in translated accesses to this field; see RDR[MT] for details. POL. Read-write. This provides duplicate access to RDR[POL] described in section 5.4. IM. Read-write. This provides duplicate access to RDR[IM] described in section 5.4.
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Link Command Register
DevA:0xC0
Default: 0040 0008h Bits Description 31:29 Slave/primary interface type. Read only. 28
Attribute: See below.
DOUI: drop on uninitialized link. Read-write. This specifies the behavior of transactions that are sent to uninitialized links. 0=Transactions that are received by the IC and forwarded to a side of the tunnel, when DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, remain in buffers awaiting transmission indefinitely (waiting for INITCPLT to be set high). 1=Transactions that are received by the IC and forwarded to a side of the tunnel, when DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, behave as if ENDOCH were high. Note: this bit is cleared by PWROK reset but not by RESET#. DEFDIR: default direction. Read-write. 0=Send secondary PCI bus master requests to the master link host as specified by DevA:0xC0[MASHST]. 1=Send secondary PCI bus master requests to the opposite side of the tunnel. MASHST: master host. Read; set and cleared by hardware. This bit indicates which link is the path to the master (or only) host bridge on the HyperTransport technology chain. 1=The hardware set this bit as a result of a write command from the B side of the tunnel to any of the bytes of DevA:0xC0[31:16]. 0=The hardware cleared this bit as a result of a write command from the A side of the tunnel to any of the bytes of DevA:0xC0[31:16]. This bit, along with DEFDIR, is used to determine the side of the tunnel to which secondary PCI bus master requests are sent.
27
26
25:21 UnitID count. Read only. Specifies the number of UnitIDs used by the IC (two). 20:16 BUID: base UnitID. Read-write. This specifies the link-protocol base UnitID. The IC's logic uses this value to determine the UnitIDs for link request and response packets. When a new value is written to this field, the response includes a UnitID that is based on the new value in this register. 15:8 Reserved. 7:0
Capabilities ID. Read only. Specifies the capabilities ID for link configuration space.
Link Configuration And Control Register
DevA:0xC4 and DevA:0xC8
DevA:0xC4 applies side A of the tunnel and DevA:0xC8 applies to side B of the tunnel. The default value for bit[5] may vary (see the definition). Default: ??11 0020h for DevA:0xC4 and ??00 0020h for DevA:0xC8.Attribute: See below. Bits Description 31 Reserved. 30:28 LWO: link width out. Read-write. Specifies the operating width of the outgoing link. Legal values are 001b (16 bits; DevA:0xC4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not connected). Note: this field is cleared by PWROK reset but not by RESET#; the default value of this field depends on the widths of the links of the connecting device, per the link specification. Note: after this field is updated, the link width does not change until either RESET# is asserted or a link disconnect sequence occurs through or LDTSTOP#. 27 Reserved.
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26:24 LWI: link width in. Read-write. Specifies the operating width of the incoming link. Legal values are 001b (16 bits; DevA:0xC4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not connected). Note: this field is cleared by PWROK reset but not by RESET#; the default value of this field depends on the widths of the links of the connecting device, per the link specification. Note: after this field is updated, the link width does not change until either RESET# is asserted or a link disconnect sequence occurs through an LDTSTOP# assertion. 23 Reserved. 22:20 Max link width out. Read only. This specifies the width of the outgoing link to be 16 bits wide for side A and 8 bits wide for side B. 19 Reserved. 18:16 Max link width in. Read only. This specifies the width of the incoming link to be 16 bits wide for side A and 8 bits wide for side B. 15 14 Reserved.
EXTCTL: extended control time during initialization. Read-write. This specifies the time in which LT[B, A]CTL is held asserted during the initialization sequence that follows an LDTSTOP# deassertion, after LR[B, A]CTL is detected asserted. 0=At least 16 bit times. 1=About 50 microseconds. Note: this bit is cleared by PWROK reset but not by RESET#. LDT3SEN: link three-state enable. Read-write. 1=During the LDTSTOP# disconnect sequence, the link transmitter signals are placed into the high impedance state and the receivers are prepared for the high impedance mode. For the receivers, this includes cutting power to the receiver differential amplifiers and ensuring that there are no resultant high-current paths in the circuits. 0=During the LDTSTOP# disconnect sequence, the link transmitter signals are driven, but in an undefined state, and the link receiver signals are assumed to be driven. Note: this bit is cleared by PWROK reset but not by RESET#. AMD recommends that this bit be set high in single-processor systems and be low in multi-processor systems. CRCERR: CRC Error. Read; set by hardware; write 1 to clear. Bit[9] applies to the upper byte of the link (DevA:0xC4 only) and bit[8] applies to the lower byte. 1=The hardware detected a CRC error on the incoming link. Note: this bit is cleared by PWROK reset but not by RESET#. TXOFF: transmitter off. Read; write 1 only. 1=No output signals on the link toggle; the input link receivers are disabled and the pins may float. ENDOCH: end of chain. Read; write 1 only or set by hardware. 1=The link is not part of the logical HyperTransport technology chain; packets which are issued or forwarded to this link are either dropped or result in an NXA error response, as appropriate; packets received from this link are ignored and CRC is not checked; if the transmitter is still enabled (TXOFF), then it drives only NOP packets with good CRC. ENDOCH may be set by writing a 1 to it or it may be set by hardware if the link is determined to be disconnected at the rising edge of RESET#. INITCPLT: initialization complete. Read only. This bit is set by hardware when low-level link initialization has successfully completed. If there is no device on the other end of the link, or if the device on the other side of the link is unable to properly perform link initialization, then the bit is not set. This bit is cleared when RESET# is asserted or after the link disconnect sequence completes after the assertion of LDTSTOP#. LKFAIL: link failure. Read; set by hardware; write 1 to clear. This bit is set high by the hardware when a CRC error is detected on the link (if enabled by CRCFEN) or if the link is not used in the system. Note: this bit is cleared by PWROK reset, not by RESET#.
13
12:10 Reserved. 9:8
7 6
5
4
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3
CRCERRCMD: CRC error command. Read-write. 1=The link transmission logic generates erroneous CRC values. 0=Transmitted CRC values match the values calculated per the link specification. This bit is intended to be used to check the CRC failure detection logic of the device on the other side of the link.
2 1
Reserved.
CRCFEN: CRC flood enable. Read-write. 1=CRC errors (in link A for DevA:0xC4[CRCFEN]; in link B for DevA:0xC8[CRCFEN]) result in sync packets to both outgoing links and the LKFAIL bit is set. 0=CRC errors do not result in sync packets or setting the LKFAIL bit.
0
Reserved.
Link Frequency Capability 0 Register
DevA:0xCC
Default: 0035 0022h. Bits Description
Attribute: See below.
31:16 FREQCAPA: link A frequency capability. Read only. These bits indicate that A side of the tunnel supports 200, 400, 600, and 800 MHz link frequencies. 15:12 Reserved. 11:8 FREQA: link A frequency. Read-write. Specifies the link side A frequency. Legal values are 0h (200 MHz), 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: this bit is cleared by PWROK reset, not by RESET#. Note: after this field is updated, the link frequency does not change until either RESET# is asserted or a link disconnect sequence occurs through LDTSTOP#. 7:0
REVISION. Read only. The IC is designed to version 1.02 of the link specification.
Link Frequency Capability 1 Register
DevA:0xD0
Default: 0035 0002h. Bits Description
Attribute: See below.
31:16 FREQCAPB: link B frequency capability. Read only. These bits indicate that that B side of the tunnel supports 200, 400, 600, and 800 MHz link frequencies. 15:12 Reserved. 11:8 FREQB: link B frequency. Read-write. Specifies the link side B frequency. Legal values are 0h (200 MHz), and 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: this bit is cleared by PWROK reset, not by RESET#. Note: after this field is updated, the link frequency does not change until either RESET# is asserted or a link disconnect sequence occurs through LDTSTOP#. 7:0
Link device feature capability indicator. Read only. These bits are set to indicate that the IC supports LDTSTOP#.
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Link Enumeration Scratchpad Register
DevA:0xD4
Default: 0000 0000h. Bits Description 31:16 Reserved.
Attribute: See below.
15:0 ESP: enumeration scratchpad. Read-write. This field controls no hardware within the IC. Note: this bit is cleared by PWROK reset, not by RESET#.
Link Non-Prefetchable Memory Space Extension Register
DevA:0xD8
Default: 0000 0000h. Bits Description 31:16 Reserved.
Attribute: Read-write.
15:8 NPUML: non-prefetchable upper memory limit. This field provides bits[39:32] of the nonprefetchable memory space address limit specified by Dev[B, A]:0x20[MEMLIM]. See Dev[B,A]:0x1C for details. 7:0
NPUMB: non-prefetchable upper memory base. This field provides bits[39:32] of the nonprefetchable memory space address base specified by Dev[B, A]:0x20[MEMBASE]. See Dev[B,A]:0x1C for details.
Link PHY Compensation Control Registers
DevA:0x[E8, E4, E0]
The link PHY circuitry includes automatic compensation that is used to adjust the electrical characteristics for the link transmitters and receivers on both sides of the tunnel. There is one compensation circuit for the receivers and one for each polarity of the transmitters. These registers provide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a fixed difference. The overrides and difference values may be different between sides A and B of the tunnel. These registers specify the compensation parameters as follows: * DevA:0xE0: transmitter rising edge (P) drive strength compensation. * DevA:0xE4: transmitter falling edge (N) drive strength compensation. * DevA:0xE8: receiver impedance compensation. For DevA:0x[E4, E0], higher values represent higher drive strength; the values range from 01h to 13h (19 steps). For DevA:0xE8, higher values represent lower impedance; the values range from 00h to 1Fh (32 steps). Note: the default state of these registers is set by PWROK reset; assertion of RESET# does not alter any of the fields. Default: See below. Bits Description 31 Attribute: See below.
Must be low. Read-write. This bit is required to be low at all times; setting it high results in undefined behavior.
30:21 Reserved. 20:16 CALCCOMP: calculated compensation value. Read only. This provides the calculated value from the auto compensation circuitry. The default value of this field is not predictable.
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15
Reserved.
14:13 BCTL: link side B PHY control value. Read-write. These two bits combine to specify the PHY compensation value that is applied to side B of the tunnel as follows: BCTL 00b 01b 10b Description Apply CALCCOMP directly as the compensation value. Apply BDATA directly as the compensation value. Apply the sum of CALCCOMP and BDATA as the compensation value. In DevA:0x[E4, E0], if the sum exceeds 13h, then 13h is applied. In DevA:0x[E8], if the sum exceeds 1Fh, then 1Fh is applied. Apply the difference of CALCCOMP minus BDATA as the compensation value. If the difference is less than 01h, then 01h is applied.
11b
The default value of this field (from PWROK reset) is controlled by the CMPOVR signal. If CMPOVR = 0, the default is 00b. If CMPOVR = 1, the default is 01b. 12:8 BDATA: link side B data value. Read-write. This value is appled to the side B of the tunnel PHY compensation as described in BCTL. The default for DevA:0x[E4, E0] is 08h. The default for DevA:0xE8 is 0Fh. 7 6:5 Reserved.
ACTL: link side A PHY control value. Read-write. These two bits combine to specify the PHY compensation value that is applied to side A of the tunnel as follows:
ACTL 00b 01b 10b
11b
Description Apply CALCCOMP directly as the compensation value. Apply ADATA directly as the compensation value. Apply the sum of CALCCOMP and ADATA as the compensation value. In DevA:0x[E4, E0], if the sum exceeds 13h, then 13h is applied. In DevA:0x[E8], if the sum exceeds 1Fh, then 1Fh is applied. Apply the difference of CALCCOMP minus ADATA as the compensation value. If the difference is less than 01h, then 01h is applied.
The default value of this field (from PWROK reset) is controlled by the CMPOVR signal. If CMPOVR = 0, the default is 00b. If CMPOVR = 1, the default is 01b. 4:0
ADATA: link side A data value. Read-write. This value is appled to the side A of the tunnel PHY compensation as described in ACTL. The default for DevA:0x[E4, E0] is 08h. The default for DevA:0xE8 is 0Fh.
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Clock Control Register
DevA:0xF0
See section 4.3.3 for details on clock gating. AMD system recommendations for System Management Action Field (SMAF) codes are: 0=ACPI C2; 1=ACPI C3; 2=FID/VID change; 3=ACPI S1; 4=ACPI S3; 5=Throttling; 6=ACPI S4/S5. AMD recommends setting this register to 0004_0008h (to gate clocks during S1). Default: 0000 0000h. Bits Description 31:19 Reserved. 18 17 16 7:0
CGEN: clock gate enable. 1=Internal clock gating, as specified by bits[7:0] of this register, is enabled. Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. ICGSMAF: internal clock gating system management action fields. Each of the bits of this field correspond to SMAF values that are captured in Stop Grant cycles from the host. For each bit, 1=When LDTSTOP# is asserted prior to a Stop Grant cycle in which the SMAF field matches the ICGSMAF bit that is asserted, then the IC power is reduced through gating of internal clocks. 0=No power reduction while LDTSTOP# is asserted. For example, if clock gating is required for SMAF values of 3 and 5, then ICGSMAF[3, 5] must be high. See section 4.3.3 for details.
Attribute: Read-write.
15:8 Reserved.
5.3
PCI-X IOAPIC Configuration Registers
These registers are located in PCI configuration space, in the first device (device A) and second device (device B), function 1. See section 5.1.2 for a description of the register naming convention.
IOAPIC Vendor And Device ID Register
Dev[B, A]:1x00
Default: 7451 1022h Bits Description 31:16 IOAPIC device ID. 15:0 Vendor ID.
Attribute: Read only.
IOAPIC Status And Command Register
Dev[B, A]:1x04
Default: 0200 0000h Bits Description 2
Attribute: See below.
31:3 Read only. These bits are fixed in their default state.
MASEN: PCI master enable. Read-write. 1=Enables IOAPIC to initiate interrupt requests to the host. Note: if Dev[B, A]:1x44[OSVISBAR]=0, then the state of this bit is ignored. Note: Dev[B, A]:1x44[IOAEN] must be high to enable interrupt requests, regardless of the state of this bit.
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1
MEMEN: memory enable. Read-write. 1=Enables access to the memory space specified by DevA:1x10. Note: if Dev[B, A]:1x44[OSVISBAR]=0, then the state of this bit is ignored. Note: Dev[B, A]:1x44[IOAEN] must be high to enable access to the register space, regardless of the state of this bit. IO enable. Read only. This bit is fixed in the low state.
0
IOAPIC Revision and Class Code Register
Dev[B, A]:1x08
Default: 0800 1001h Bits Description 7:0
REVISION.
Attribute: Read only.
31:8 CLASSCODE. Provides the IOAPIC class code.
IOAPIC Device BIST-Header-Latency-Cache Register
Dev[B, A]:1x0C
Default: 0000 0000h Bits Description
Attribute: Read only.
31:24 BIST. These bits are fixed at their default values. 23:16 HEADER. These bits are fixed at their default values. 15:8 LATENCY. These bits are fixed at their default values. 7:0
CACHE. These bits are fixed at their default values.
IOAPIC Base Address Register
Dev[B, A]:1x10 and Dev[B, A]:1x48
Offsets 10h and 48h provide access to the same 8-byte register. Offset 48h is always accessible. However, offset 10h can be disabled from read and write access through Dev[B, A]:1x44[OSVISBAR]. Default: 0000 0000 0000 0004h Bits Description Attribute: See below.
63:12 IOABAR: IOAPIC base address register. Read-write. These bits specify the address space of the IOAPIC register set, IOAxx. Note: bits[63:40] are required to be programmed low; setting any of these bits high results in undefined behavior. 11:0 Hardwired. Read only. These bits are all hardwired to their default state to indicate a 4K byte block of 64-bit, non-prefetchable memory space.
IOAPIC Device Subsystem ID and Subsystem Vendor ID Register
Dev[B, A]:1x2C
Default: 0000 0000h Bits Description
Attribute: Read; write once.
31:16 Subsystem ID. This field controls no hardware. 15:0 Subsystem vendor ID. This field controls no hardware.
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IOAPIC Control Register
Dev[B, A]:1x44
Default: 0000 0000h Bits Description 31:2 Reserved. 1 0
Attribute: Read-write.
IOAEN: IOAPIC enable. 1=Access to the IOAPIC registers pointed to by Dev[B, A]:1x10/48 is enabled and the IOAPIC is enabled to generate interrupt requests. OSVISBAR: operating system visible base address register. 0=Dev[B, A]:1x10 is not visible; reads provide all zeros and writes are ignored. Also, the state of Dev[B, A]:1x04[MASEN, MEMEN] are ignored. 1=The IOAPIC BAR is read-write accessible through Dev[B, A]:1x10 and Dev[B, A]:1x04[MASEN, MEMEN] function as specified.
IOAPIC Base Address Register
Dev[B, A]:1x48
Offsets 10h and 48h provide access to the same 8-byte register. Offset 48h is always accessible. However, offset 10h can be disabled from read and write access through Dev[B, A]:1x44[OSVISBAR]. See offset 10h for the register specification.
5.4
IOAPIC Registers
These registers are located in IOAxx memory space. The base address register for these registers is Dev[B, A]:1x10/48. See section 5.1.2 for a description of the register naming convention. See also section 4.5.2 for more details about interrupt operation. See also Dev[B, A]:0x[BC, B8] for a description of alternative access to these registers and expanded programmability. The IOAPIC register set supports 4 interrupts and corresponding redirection registers. The space is indexed through two memory-mapped ports: IOA00 (IOAxx at offset 00h) provides the 8-bit index register; IOA10h (IOAxx at offset 10h) provides the 32-bit data port. Writes to IOA10h, the 32-bit data port, must be 32-bit, aligned accesses; other than 32-bit writes result in undefined behavior. Reads provide all four bytes regardless of the byte enables. The index written to IOA00 selects one of the following: IOA00[7:0] Description 00h 01h 02h
APIC ID register. Bits[27:24] are read-write; they control no hardware. All other bits are reserved. IOAPIC version register. Read only. These bits are fixed in their default state. IOAPIC arbitration ID register. Bits[27:24] are read-write; they control no hardware. All other bits are reserved.
Default
0000 0000h 0003 0011h 0000 0000h
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10h-17h
bits[63:32] = RDR: redirection registers. Each of the 4 redirection registers utilizes two 0000 0000h. indexes. Bits[63:32] are accessed through the odd indexes and bits[31:0] are accessed through the even indexes. They are mapped to the PCI interrupt pins as bits[31:0] = follows: 0001 0000h. IOA00 for bits[31:0] IOA00 for bits[63:32] Pin [B, A]_PIRQA# 10h 11h [B, A]_PIRQB# 12h 13h [B, A]_PIRQC# 14h 15h [B, A]_PIRQD# 16h 17h Reserved.
18h-FFh
RDR: the redirection registers are defined as follows: Bits Description
63:56 DEST: destination. Read-write. IntrInfo[15:8] in the link interrupt request packet. In physical mode, bits[59:56] specify the APIC ID of the target processor. In logical mode bits[63:56] specify a set of processors. 55:17 Reserved. 16
IM: interrupt mask. Read-write. 1=Interrupt is masked. When the interrupt is specified to be in edge-sensitive mode and this bit transitions from 1 to 0, then no interrupt request is generated regardless of the state of the interrupt line. When the interrupt is specified to be in level-sensitive mode and the interrupt line is in the asserted state, then when this bit transitions from 1 to 0, an interrupt request is generated. The state of this bit is also used for the NIOAIRQ[D:A]# pins; see Dev[B, A]:0x40[NIOAMODE]. TM: trigger mode. Read-write. IntrInfo[5] in the link interrupt request packet. 0=Edge sensitive. 1=Level sensitive. Normally, it is expected that this bit be programmed for level-sensitive interrupts. Note: this bit is ignored for delivery modes of SMI, NMI, Init, and ExtINT, which are always treated as edge sensitive. IRR: interrupt request receipt. Read only. This bit is not defined for edge-triggered interrupts. For level-triggered interrupts, this bit is set by the hardware after an interrupt is detected. It is cleared by receipt of EOI as specified in section 4.5.2. . POL: polarity. Read-write. 0=Active high for level-sensitive interrupts and rising edge for edgesensitive interrupts. 1=Active low for level-sensitive interrupts and falling edge for edge-sensitive interrupts. This bit applies to the polarity of the [B, A]PIRQ[D:A]# pins as they enter the IC. Normally, it is expected that this bit be programmed for active low interrupts. This bit has no effect on the NIOAIRQ[D, C, B, A]# pins. DS: delivery status. Read only. 0=Idle. 1=Interrupt message pending. DM: destination mode. Read-write. IntrInfo[6] in the link interrupt request packet. 0=Physical mode. 1=Logical mode.
15
14
13
12 11
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10:8 MT: message type. Read-write. These bits are physically located in IDRDR[MT] (See Dev[B, A]:0x[BC, B8]). Accesses to this field result in translated accesses to the register bits in IDRDR[MT]. The value in IDRDR[MT] becomes the IntrInfo[4:2] field in link interrupt request packets. The translation is as follows: Access to RDR[MT] 000b 001b 010b 011b 100b 101b 110b 111b Interrupt type Fixed Lowest priority SMI Reserved NMI Init Reserved ExtINT Value in IDRDR[MT] 000b 001b 010b 111b 011b 100b 101b 110b
So, for example, a write of 111b to RDR[MT] results in a write of 110b in IDRDR[MT]. Subsequent reads of RDR[MT] provide 111b. Subsequent reads of IDRDR[MT] provide 110b. The value placed in link interrupt request packets is as specified in IDRDR[MT] (110b). A write of 110b in IDRDR[MT] would be read as 111b through RDR[MT]. 7:0
IV: interrupt vector. Read-write. IntrInfo[23:16] in the link interrupt request packet.
5.5
SHPC Working Registers
These registers are accessed through either: * Indexed configuration space (see Dev[B, A]:0x90[SELECT] and Dev[B, A]:0x94[DATA]), or * Non-indexed memory space (see SHPC[B, A]:00). See section 5.1.2 for a description of the register naming convention. If DevA:0x48[HPENA] = 0 then the SHPCA:XX registers are all reserved; if DevA:0x48[HPENB] = 0 then the SHPCB:XX registers are all reserved.
SHPC Base Offset Register
SHPC[B, A]:00
Default: 0000 0000h. Bits Description
Attribute: Read only.
31:0 BASE_OFFSET. This register is hard-wired low to indicate that the memory-space base address of the SHPC register set is specified only by Dev[B,A]:0x10[SHPCBAR].
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SHPC Slots Available Register I
SHPC[B, A]:04
Default: 0000 0000h Bits Description 31:29 Reserved.
Attribute: Write once.
28:24 N_133PCIX. Indicates maximum number of hot plug slots available to be enabled when the bus is running at 133 MHz in PCI-X mode. 23:21 Reserved. 20:16 N_100PCIX. Indicates maximum number of hot plug slots available to be enabled when the bus is running at 100 MHz in PCI-X mode. 15:13 Reserved. 12:8 N_66PCIX. Indicates maximum number of hot plug slots available to be enabled when the bus is running at 66 MHz in PCI-X mode. 7:5 4:0 Reserved.
N_33CONV. Indicates maximum number of hot plug slots available to be enabled when the bus is running at 33 MHz in conventional PCI mode.
SHPC Slots Available Register II
SHPC[B, A]:08
Default: 0000 0000h Bits Description 31:5 Reserved. 4:0
Attribute: Write once.
N_66CONV. Indicates maximum number of hot plug slots available to be enabled when the bus is running at 66 MHz in conventional PCI mode.
SHPC Slot Configuration Register
SHPC[B, A]:0C
Default: 0000 0000h Bits Description 31 30 29
Attribute: Write once.
ABI: attention button implemented. 1=Hot plug slots implement the attention button. 0=Hot plug slots do not implement the attention button. MRLSI: MRL sensor implemented. 1=Hot plug slots implement the MRL sensor. 0=Hot plug slots do not implement the MRL sensor. PSN_UP: physical slot number up/down. 1=Each external slot label increments by 1 from the value in SHPC[B, A]:0C[PSN]. 0=Each external slot label decrements by 1 from the value in SHPC[B, A]:0C[PSN].
28:27 Reserved. 26:16 PSN: physical slot number. Specifies the physical slot number of the device specified by SHPC[B, A]:0C[FDN]. 15:13 Reserved. 12:8 FDN: first device number. Specifies the device number assigned to the first hot plug slot on the secondary bridge bus.
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7:5 4:0
Reserved.
NSI: number of slots implemented. Specifies the number of hot plug slots on the bridge.
SHPC Secondary Bus Configuration Register
SHPC[B, A]:10
Default: 0100 0000h Bits Description 23:3 Reserved. 2:0
Attribute: Read only.
31:24 SHPC Programming Interface. Identifies the format of the SHPC Working Register set.
MODE. Indicates the current speed and mode at which the secondary bridge bus operates. 000b = 33 MHz conventional mode. 001b = 66 MHz conventional mode. 010b = 66 MHz PCI-X mode. 011b = 100 MHz PCI-X mode. 100b = 133 MHz PCI-X mode. 101b, 110b, and 111b are reserved.
SHPC Command Register
SHPC[B, A]:14
Writes to SHPC[B, A]:14 are ignored if SHPC[B, A]:16[BSY] = 1. Default: 0000h Bits Description 15:13 Reserved. 12:8 TGT: target slot. Specifies the slot to which SHPC[B, A]:14[CMD] is applied for the Slot Operation command. 7:0
CMD: SHPC command code. Specifies the SHPC command to be executed (see below). CMD[7:0]
Attribute: Read-write.
Command Name
Slot Operation Set Bus Segment Speed/Mode Power Only All Slots Enable All Slots
0 0 0 0
0 1 1 1
Attention Indicator 0 0 0 0 0 0
Power Indicator 0 1 1 0 0
Slot State
Bus Speed/Mode 0 0 0 1
Decodings for SHPC command code fields are: * Attention Indicator and Power Indicator specify LED states. 00b=No change; 01b=On; 10b=Blink; 11b=Off. * Slot State specifies the command to the slot. 00b=No Change; 01b=Power only; 10b=Enable slot; 11b=Disable slot. * Bus Speed/Mode specifies the bridge speed and mode. See SHPC[B, A]:10[MODE] for the encoding.
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AMD-8131TM PCI-X Tunnel Data Sheet
SHPC Status Register
SHPC[B, A]:16
The Controller Command Error Code field consists of SHPC[B, A]:16[INVSM_ERR, INVCMD_ERR, MRLO_ERR]. No bits or one bit of the Controller Command Error Code field may be updated when SHPC[B, A]:16[BSY] transitions from 1 to 0, indicating command completion with an error. If a bit in the Controller Command Error Code field is set, then it remains set until the next 1 to 0 transition of BSY. Default: 0000h Bits Description 15:4 Reserved. 3
INVSM_ERR: Invalid Speed/Mode. This is set high when one of the following errors occurs: * The target slot specified by SHPC[B, A]:14[TGT] is not capable of running at the current speed or mode when the Slot Operation Command Enable command is issued. * A slot on the bus is not capable of running at the current bus speed or mode when the Enable All Slots Command is issued. * An enabled slot on the bus segment is not capable of running at the requested bus speed or mode when the Set Bus Segment Speed/Mode Command is issued. * The Set Bus Segment Speed/Mode Command is issued when the number of slots available at the requested bus speed or mode (specified by SHPC[B, A]:[08, 04]) is greater than zero and less than the number of slots enabled. INVCMD_ERR: invalid SHPC command. This is set high when one of the following errors occurs: * A reserved command code is used. * The target slot specified by SHPC[B, A]:14[TGT] is zero or is greater than the SHPC[B, A]:0C[NSI] for any Slot Operation Command. * The target slot specified by SHPC[B, A]:14[TGT] is greater than the number of slots available at the current bus speed or mode (specified by SHPC[B, A]:[08, 04]) when Slot Operation Command Enable is issued. * The target slot specified by SHPC[B, A]:14[TGT] is enabled when Slot Operation Command Power Only is issued. * One or more slots on the bus segment are already enabled when Power Only All Slots Command or Enable All Slots Command is issued. * The Set Bus Segment Speed/Mode Command is issued when SHPC[B, A]:[08, 04] indicate no slots are available at the requested speed or mode. MRLO_ERR: MRL open. 1=The MRL of the target slot specified by SHPC[B, A]:14[TGT] was open when Slot Operation Command Power Only or Slot Operation Command Enable was issued. BSY: Controller Busy. 1=An SHPC command (see SHPC[B, A]:14) is in progress.
Attribute: Read only.
2
1 0
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AMD-8131TM PCI-X Tunnel Data Sheet
SHPC Interrupt Locator Register
SHPC[B, A]:18
Default: 0000 0000h Bits Description 31:5 Reserved. 4:1
Attribute: Read only.
IP[4:1]: slot interrupt pending. Each bit n of this field corresponds to slot n. 1=A slot status bit capable of generating interrupts is set and the corresponding interrupt mask is 0. Slot status bits capable of generating interrupts are SHPC[B, A]:[30, 2C, 28, 24][CPC_STS, IPF_STS, ABP_STS, MRLSC_STS, CPF_STS]. The corresponding interrupt masks are SHPC[B, A]:[30, 2C, 28, 24][CP_IM, IPF_IM, AB_IM, MRLS_IM, CPF_IM]. CC_IP: command complete interrupt pending. 1=SHPC[B, A]:20[CC_STS] is 1 and SHPC[B, A]:20[CC_IM] is 0.
0
SHPC SERR Locator Register
SHPC[B, A]:1C
Default: 0000 0000h Bits Description 31:5 Reserved. 4:1
Attribute: Read only.
SERRP[4:1]: slot SERR pending. Each bit n of this field corresponds to slot n. 1=A slot status bit capable of generating SERR is set and the corresponding SERR mask is 0. Slot status bits capable of generating SERR are SHPC[B, A]:[30, 2C, 28, 24][MRLSC_STS, CPF_STS]. The corresponding SERR masks are SHPC[B, A]:[30, 2C, 28, 24][MRLS_SERRM, CPF_SERRM]. A_SERRP: arbiter SERR pending. 1=SHPC[B, A]:20[ATOUT_STS] is 1 and SHPC[B, A]:20[A_SERRM] is 0.
0
SHPC SERR-INT Register
SHPC[B, A]:20
The wakeup signal shown below sets Dev[B, A]:0x9C[PME_STS]. SHPC_WAKEUP = (SHPC[B, A]:18[IP] != 0000b) | ~SHPC[B, A]:20[CC_IM] & SHPC[B, A]:20[CC_STS]; The SHPC interrupt shown below is routed to the [B, A]_PIRQA# pin. SHPC_INTR = ~SHPC[B, A]:20[GIM] & SHPC_WAKEUP; The SHPC system error shown below sets Dev[B, A]:0x1C[RSE] (see also Dev[B, A]:0x3C[SERREN]). SHPC_SERR = ~SHPC[B, A]:20[GSERRM] & ( (SHPC[B, A]:1C[SERRP] != 0000b) | ~SHPC[B, A]:20[A_SERRM] & SHPC[B, A]:20[ATOUT_STS]);
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Default: 0000 000Fh Bits Description 31:18 Reserved. 17
Attribute: See below.
ATOUT_STS: arbiter timeout status. Read; set by hardware; write 1 to clear. Set when an arbiter timeout is detected by the SHPC logic. The arbiter timeout occurs when the PCI bus is requested (from the internal arbiter) for a hot plug operation and it is not granted for 2^23 [B, A]_PCLK cycles. CC_STS: command completion status. Read; set by hardware; write 1 to clear. Set when an SHPC[B, A]:16[BSY] transition from 1 to 0 is detected. A_SERRM: arbiter SERR mask. Read-write. 1=SERR indication for arbiter timeout is disabled. CC_IM: command complete interrupt mask. Read-write. 1=SHPC interrupt generation for command completion is disabled. GSERRM: global SERR mask. Read-write. 1=SERR indication is disabled. GIM: global interrupt mask. Read-write. 1=SHPC interrupt generation is disabled.
16
15:4 Reserved. 3 2 1 0
SHPC Logical Slot Registers
SHPC[B, A]:[30, 2C, 28, 24]
The offset for the SHPC Logical Slot Register (or LSR) for slot 1 is 24h, for slot 2 is 28h, for slot 3 is 2Ch, and for slot 4 is 30h. "LSR" is used instead of SHPC[B, A]:[30, 2C, 28, 24] in the description below. See SHPC[B, A]:20 for information about how these registers may affect interrupts, events, and system errors. Default: 7F00 3F3Fh Bits Description 31 30 29 28 27 26 25 24 Reserved.
CPF_SERRM: connected power fault SERR mask. Read-write. 1=SERR generation is disabled when LSR[CPF_STS] is set. 0=SERR generation is enabled when LSR[CPF_STS] is set. MRLS_SERRM: MRL sensor SERR mask. Read-write. 1=SERR generation is disabled when LSR[MRLSC_STS] is set. 0=SERR generation is enabled when LSR[MRLSC_STS] is set. CPF_IM: connected power fault interrupt mask. Read-write. 1=Interrupt generation is disabled when LSR[CPF_STS] is set. 0=Interrupt generation is enabled when LSR[CPF_STS] is set. MRLS_IM: MRL sensor interrupt mask. Read-write. 1=Interrupt generation is disabled when LSR[MRLSC_STS] is set. 0=Interrupt generation is enabled when LSR[MRLSC_STS] is set. AB_IM: attention button interrupt mask. Read-write. 1=Interrupt generation is disabled when LSR[ABP_STS] is set. 0=Interrupt generation is enabled when LSR[ABP_STS] is set. IPF_IM: isolate power fault interrupt mask. Read-write. Read-write. 1=Interrupt generation is disabled when LSR[IPF_STS] is set. 0=Interrupt generation is enabled when LSR[IPF_STS] is set. CP_IM: card presence interrupt mask. Read-write. 1=Interrupt generation is disabled when LSR[CPC_STS] is set. 0=Interrupt generation is enabled when LSR[CPC_STS] is set. CPF_STS: connected power fault status. Read; set by hardware; write 1 to clear. Set when LSR[PF] changes from 0 to 1 while LSR[SS] = 10b (slot is enabled).
Attribute: See below.
23:21 Reserved. 20
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19 18 17 16
MRLSC_STS: MRL sensor change status. Read; set by hardware; write 1 to clear. Set when LSR[MRLS] changes its value. ABP_STS: attention button press status. Read; set by hardware; write 1 to clear. Set when LSR[AB] transitions from 0 to 1. IPF_STS: isolated power fault status. Read; set by hardware; write 1 to clear. Set when LSR[PF] changes from 0 to 1 while LSR[SS] != 10b (slot is not in the enabled state). . CPC_STS: card presence change status. Read; set by hardware; write 1 to clear. Set when LSR[PRSNT1_2] field changes value.
15:14 Reserved. 13:12 PCI-X_CAP: PCI-X capability. Read-only. Reflects the current PCI-X capability of the add-incard. These bits are not valid if the slot is empty. 00b = Conventional PCI. 01b = 66 MHz PCI-X mode. 10b = Reserved. 11b = 133 MHz PCI-X mode. 11:10 PRSNT1_2: PRSNT1#/PRSNT2#. Read-only. Reflects the current debounced state of the PRSNT1# and PRSNT2# pins on the slot. 00b = Card present; 7.5W. 01b = Card present; 15W. 10b = Card present; 25W. 11b = Slot Empty. 9
M66_CAP: 66 MHz capable. Read-only. This bit is valid only when the slot is occupied and powered. 1=Add-in card is capable of running at 66 MHz conventional mode. 0=Add-in-card is capable of running at 33 MHz conventional mode only. MRLS: MRL sensor. Read-only. Reflects the current state of the debounced MRL sensor. 1=MRL sensor is open. 0=MRL sensor is closed. AB: attention button. Read-only. Reflects the current state of the debounced attention button. 1=Attention button is being pressed. 0=Attention button is released. PF: power fault. Read-only. Reflects the current state of the power fault latch in the slot power control circuitry. 1=Power fault (isolated or connected) is detected. AIS: attention indicator state. Read-only. Reflects the current state of the attention indicator. 00b = reserved. 01b = on. 10b = blink. 11b = off. PIS: power indicator state. Read-only. Reflects the cuttent state of the power indicator. 00b = reserved. 01b = on. 10b = blink. 11b = off. SS: slot state. Read-only. Reflects the current state of the slot. 00b = reserved. 01b = powered only. 10b = enabled. 11b = disabled.
8 7 6 5:4 3:2 1:0
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AMD-8131TM PCI-X Tunnel Data Sheet
6 6.1
Electrical Data Absolute Ratings
The IC is not designed to operate beyond the parameters shown in the following table.
Parameter VDD12[B, A] VDD18, VDDA18 VDD33 TCASE (Under Bias) TSTORAGE -65 C Minimum -0.5 V -0.5 V -0.5 V Maximum 1.7 V 2.0 V 3.6 V 85 C 150 C Comments
Table 11: Absolute maximum ratings.
6.2 Operating Ranges
The IC is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in the following table.
Parameter VDD12[B, A] VDD18, VDDA18 VDDA18 peak-to-peak noise VDD33 TCASE (Under Bias) 3.135 3.3 Minimum 1.14 1.71 Typical 1.2 1.8 Maximum Units 1.26 1.89 50 3.465 85 V V mV V deg C Maximum sinusoidal amplitude at frequency range from 50 KHz to 20 MHz. Comments
Table 12: Operating ranges.
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6.3
DC Characteristics
See the HyperTransportTM Technology Electrical Specification for the DC characteristics of link signals. The following table shows current consumption in amps and power in watts for each power plane. Unless otherwise noted, values assume that both bridges are operating at 133 MHz.
Typical Parameter Description VDD12A current, power VDD12B current, power VDD18 current, power; operational Current 0.13 A 0.07 A 1.90 A Power 0.16 W 0.08 W 3.42 W 0.54 W 0.94 W 0.04 W 1.65 W 5.4 W 0.19 A 0.09 A 2.40 A 0.43 A 0.75 A 0.03 A 0.60 A Max Current Power 0.24 W 0.12 W 4.54 W 0.82 W 1.42 W 0.06 W 2.08 W 7.0 W
VDD18 current, power; internal clock gated mode (see section 4.3.3); both 0.30 A bridges operating at 66 MHz. VDD18 current, power; internal clock gated mode (see section 4.3.3); both 0.52 A bridges operating at 133 MHz. VDDA18 current, power VDD33 current, power; assumes no current load on PCI bus signals Total power; operational (no clock gating) 0.02 A 0.50 A
Table 13: Current and power consumption.
The following table shows DC characteristics for signals on the VDD33 power plane.
Symbol VIL VIH VOL VOH ILI CIN VXCL VXCM VXCH Parameter Description Input low voltage Input high voltage Output low voltage; IOUT = 1.5 mA Output high voltage; IOUT = -0.5 mA Input leakage current Input capacitance [B, A]_PCIXCAP voltage for low state [B, A]_PCIXCAP voltage for mid state [B, A]_PCIXCAP voltage for high state 0.25 VDD33 0.85 VDD33 0.9 VDD33 +/- 10 8 0.15 VDD33 0.70 VDD33 Min -0.5 0.5 VDD33 Max 0.35 VDD33 Units V Comments
0.5 + VDD33 V 0.1 VDD33 V V uA pF V V V
Table 14: DC characteristics for signals on the VDD33 power plane.
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6.4
AC Characteristics
See the HyperTransport Technology Electrical Specification for the AC characteristics of link signals, PWROK, RESET#, and LDTSTOP#. The following table shows AC requirements for REFCLK.
Symbol tREF tREFCJ tREFPJ tREFSW tREFSS Parameter Description REFCLK cycle time REFCLK cycle to cycle jitter; difference in the period of any two adjacent REFCLK cycles REFCLK period jitter; difference between the nominal period and the period of any REFCLK cycle REFCLK slew rate REFCLK 33 KHz spread spectrum frequency change from tREF -0.300 1 -0.5 Min 15 Max 18 0.250 Units Comments ns ns
+0.300 ns 4 0 V/ns %
Table 15: AC requirements for REFCLK.
The following table shows AC specification data for PCI clocks.
Symbol tCYC tHIGH tLOW tSLEW Parameter Description [B, A]_PCLK[4:0] cycle time [B, A]_PCLK[4:0] high time [B, A]_PCLK[4:0] low time [B, A]_PCLK[4:0] slew rate 133 MHz 7.5 3 3 1.5 4 100 MHz 10 4 4 1.5 4 66 MHz 15 6 6 1.5 4 33 MHz 30 11 11 1.5 4 Units Comments ns ns ns V/ns Min Max Min Max Min Max Min Max
Table 16: AC data for PCI clocks.
The following table shows general AC specification data. "PCLK" refers to [B, A]_PCLK[4:0].
Symbol Parameter Description ConvenConven- Units Comments PCI-X tional PCI tional PCI 133, 100, 66 66 MHz 33 MHz MHz Min Max Min Max Min Max Tval Ton Toff Tsu Th PCLK to signal valid delay PCLK to signal active delay PCLK to signal float delay Input setup time to PCLK Input hold time from PCLK 1.2 0.5 0.7 0 7 3 0 3.8 2 2 14 7 0 6 2 2 28 11 ns ns ns ns ns
Table 17: AC data for PCI bus.
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7
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC VSS FREE 12 FREE 18 B_AD 35 B_AD 38 B_AD 44 B_AD 50 B_AD 53 B_AD 59
Ball Designations
2 3 4 5 VSS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VSS VSS VSS VSS VSS VSS 27 CMP OVR STRAP RESET L2 # LDT PWR STOP# OK TEST VSS VSS VSS REF CLK VSS LTBCA D_P0 28 29 A B C D E F G H J K L M N P R T U V LDT VSS COMP1 LTACA LTACA LTACA LTACA LTACL LTACL LTACA LTACA LTACA LTACA LRACT LRACT LRACA LRACA LRACA LRACA LRACA LRACA LRACA LRACA D_P0 D_N0 D_P2 D_N2 K0_P K0_N D_P5 D_N5 D_P7 D_N7 L_N L_P D_N6 D_P6 D_N4 D_P4 D_N3 D_P3 D_N1 D_P1 VSS LTACA VDD18 LTACA D_P1 D_P3 VSS LTACA VDD18 LTACA D_P4 D_P6 VSS LTACT VDD18 LRACA L_P0 D_N7 VSS LRACA VDD18 LRACL D_N5 K0_N VSS LRACA VDD18 LRACA D_N2 D_N0
LDT VSS LDT VSS COMP2 COMP0 VSS FREE 10 FREE 19 B_AD 34 VSS B_AD 43 B_AD 49 VSS B_AD 58 LDT VSS COMP3 VSS FREE 13 B_AD 33 FREE1 FREE 14 VSS VSS VSS
LTACA LTACA LTACA LTACA LTACL LTACA LTACA LTACA LTACA LTACT RSVD3 LRACA LRACA LRACA LRACA LRACL LRACA LRACA LRACA LRACA D_N8 D_N1 D_N10 D_N3 K1_N D_N4 D_N13 D_N6 D_N15 L_N0 D_P7 D_P14 D_P5 D_P12 K0_P D_P11 D_P2 D_P9 D_P0 LTACA VDD18 LTACA D_P8 D_P10 VSS LTACL VDD18 LTACA K1_P D_P13 VSS LTACA VDD18 RSVD2 D_P15 VSS LRACA VDD18 LRACA D_N14 D_N12 VSS LRACA VDD18 LRACA D_N11 D_N9 VSS
LTACA LTACA LTACA LTACA LTACA LTACA LTACA LTACA RSVD0 RSVD1 LRACA LRACA LRACA LRACA LRACL LRACL LRACA LRACA LRACA LRACA D_P9 D_N9 D_P11 D_N11 D_P12 D_N12 D_P14 D_N14 D_N15 D_P15 D_N13 D_P13 K1_N K1_P D_N10 D_P10 D_N8 D_P8 VSS VSS B_AD 39 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VSS VDD18 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VDD18 VSS VDD12 A VSS VDD12 A VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VSS VDD18 VSS VDD12 A VSS VDD12 A VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VSS VDD33 VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VDD33 VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS A_AD 48 A_AD 49 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VDD33 VSS A_AD 54 VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VSS VDD18 VSS VDD12 A VSS VDD12 A VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VDD33 VDD18 VSS VDD12 A VSS VDD12 A VSS VDD12 B VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD33 VSS VDD33 VSS VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD33 VSS VDD33 VDD18 VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD33 VSS VDD33 VSS VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD12 B VSS VDD33 VSS VDD33 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD33 VSS VDD33 VSS VSS VDD18 NIOA IRQA#
B_AD FREE5 32
LTBCA LTBCA LTBCA D_N1 D_P1 D_N0 VSS VDD18 LTBCA D_P2
B_AD VDD33 B_AD 37 36 B_AD 42 B_AD 48 B_AD 41 B_AD 47 B_AD 40 B_AD 46
VDD18 NIOA NIOA NIOA IRQB# IRQD# IRQC# VSS VDD18
VDD33 STRAP VDD18 LTBCA LTBCA LTBCA L3 D_N3 D_P3 D_N2 VSS HPSOD HPSIL# RSVD4 VSS VSS LTBCL K0_P
B_AD VDD33 45 VSS
B_AD VDD33 B_AD VDD33 52 51 B_AD 57 B_AD 56 B_AD 62 B_AD 55 B_AD 61
VSS A_COM RSVD5 PAT
LTBCA LTBCA LTBCL D_N4 D_P4 K0_N
B_AD VDD33 54 B_AD 60 VSS VSS VDD33 VSS
VDD18 RSVD6 RSVD7 A_REQ RSVD8 VDD18 LTBCA 4# D_P5 VSS A_PLL A_PLL VDD18 LTBCA LTBCA LTBCA CLKO CLKI D_N6 D_P6 D_N5 VSS LTBCA D_P7
B_CBE B_PAR B_AD _L4 64 63 B_CBE _L7 VSS
B_CBE VDD33 B_CBE _L6 _L5
VDD18 A_GNT A_ RSVD9 RSVD 4# PCLK4 10 VSS VDD18 VSS A_ A_GNT PCLK3 3# VSS
B_AD3 B_AD2 B_AD1 B_AD0 B_ACK B_REQ 64# 64#
LTBCT LTBCT LTBCA L_N L_P D_N7
B_AD4 B_AD5 B_AD6 B_AD7 B_CBE B_AD8 VDD33 _L0 B_AD9 VSS B_M66 VDD33 B_AD VDD33 EN 10 B_AD 13 B_AD 14 VSS
A_ A_GNT A_REQ RSVD VDD18 LRBCT PCLK2 2# 3# 11 L_N A_ A_REQ VDD18 LRBCA LRBCA LRBCT PCLK1 2# D_P7 D_N7 L_P VSS LRBCA D_N6
B_AD1 B_AD 1 12 B_PAR B_ TRDY#
B_AD B_CBE VDD33 15 _L1 VSS VDD33 VSS
VDD18 A_PIRQ A_GNT RSVD RSVD A# 1# 12 13 VSS A_REQ A_PIRQ VSS 1# B#
B_ B_ B_ B_PCIX B_DEV SERR# PERR# STOP# CAP SEL# VSS B_IRDY VDD33 B_FRA # ME# B_AD 17 B_AD 18 B_AD 19 VSS B_AD 20
LRBCA LRBCA LRBCA D_P5 D_N5 D_P6
VDD18 RSVD RSVD RSVD RSVD VDD18 LRBCA W 14 15 16 17 D_N4 VSS VDD18 RSVD VDD18 LRBCL LRBCL LRBCA 18 K0_P K0_N D_P4 VSS Y
B_CBE B_AD _L2 16 B_AD 21 B_AD 26 B_AD 29 B_AD 22 VSS B_AD 30
B_AD B_CBE B_AD 23 _L3 24
B_AD VDD33 25 VSS
VDD18 A_PIRQ RSVD RSVD RSVD C# 19 20 21 VSS A_ A_PIRQ VSS PCLK0 D#
LRBCA AA D_N3
B_AD VDD33 B_AD VDD33 27 28
LRBCA LRBCA LRBCA AB D_P2 D_N2 D_P3
B_AD B_REQ B_GNT B_ VDD33 31 0# 0# PCLK0
VDD33 A_REQ A_GNT A_PRE RSVD VDD18 LRBCA AC 0# 0# SET# 22 D_N1
AD B_PRE B_PIRQ B_PIRQ B_PIRQ FREE6 B_PME A_PME SET# D# C# B# # # AE B_PIRQ VSS A#
FREE FREE8 A_AD VDD33 A_AD 15 33 42 VSS VSS VSS VSS A_AD 34 A_AD 39 A_AD 43
A_AD6 A_CBE VDD33 A_AD6 A_AD 2 _L7 10
A_ A_FRA VDD33 A_AD VDD18 LRBCA LRBCA LRBCA AD PERR# ME# 23 D_P0 D_N0 D_P1 A_AD 22 VSS VSS VSS VSS VDDA 18 AE AF
P_CAL VDD33 FREE B_PLL B_PLL B_REQ FREE 17 CLKI CLKO 4# 22
A_AD A_CBE A_AD0 A_AD5 A_M66 A_AD A_ A_IRDY A_AD 61 _L6 EN 13 SERR# # 17
AF B_REQ P_CAL B_GNT B_ VDD33 B_REQ B_REQ VDD33 B_ 1# # 1# PCLK1 2# 3# PCLK4 AG AH AJ 1 2 FREE 16 FREE VDD33 20 VSS NC2 NC0 NC3 NC1 VSS B_GNT B_GNT B_GNT FREE3 2# 3# 4# B_ B_ PCLK2 PCLK3 VSS VSS
A_AD VDD33 A_AD 35 44 A_AD 36 A_AD 37 A_AD 38 11 A_AD 40 VSS A_AD 41 12 A_AD 45 A_AD 46 A_AD 47 13
A_AD VDD33 A_AD A_CBE VDD33 A_AD4 A_AD9 VDD33 A_PAR A_ VDD33 A_AD 50 60 _L5 TRDY# 21 A_AD 51 A_AD 52 A_AD 53 14 A_AD 55 VSS A_AD 56 15 A_AD A_CBE A_ACK A_AD3 A_AD8 A_AD A_CBE A_DEV A_AD 59 _L4 64# 12 _L1 SEL# 16 A_AD A_PAR 58 64 A_AD 57 16 VSS A_AD2 A_CBE _L0 VSS A_AD A_PCIX VSS 15 CAP A_AD 20 A_AD 19
A_AD VDD33 A_AD 26 31 A_AD 25 A_AD 24 A_AD 28 VSS A_AD 30 A_AD 29
VDDA AG 18 AH AJ
FREE9 FREE FREE2 HPSIC HPSOC FREE4 FREE7 A_AD 21 32 3 4 5 6 7 8 9 10
A_AD A_REQ A_AD1 A_AD7 A_AD1 A_AD A_ A_CBE A_AD A_CBE A_AD 63 64# 1 14 STOP# _L2 18 _L3 27 17 18 19 20 21 22 23 24 25 26 27 28 29
Top side view
Figure 13: Ball designations.
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AMD-8131TM PCI-X Tunnel Data Sheet
Alphabetical listing of signals and corresponding BGA designators.
Signal name A_ACK64# A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 A_AD32 A_AD33 A_AD34 A_AD35 A_AD36 A_AD37 A_AD38 A_AD39 A_AD40 A_AD41 A_AD42 A_AD43 A_AD44 A_AD45 A_AD46 A_AD47 A_AD48 A_AD49 A_AD50 Ball AG18 AE18 AJ19 AH19 AG19 AF19 AE19 AD19 AJ20 AG20 AF20 AD20 AJ21 AG21 AE21 AJ22 AH22 AG24 AE24 AJ25 AH25 AG25 AF25 AE25 AD25 AH26 AG26 AF26 AJ27 AG27 AH28 AG28 AF28 AJ10 AD11 AE11 AF11 AG11 AH11 AJ11 AE12 AG12 AJ12 AD13 AE13 AF13 AG13 AH13 AJ13 AD14 AE14 AF14 Signal name A_AD51 A_AD52 A_AD53 A_AD54 A_AD55 A_AD56 A_AD57 A_AD58 A_AD59 A_AD60 A_AD61 A_AD62 A_AD63 A_CBE_L0 A_CBE_L1 A_CBE_L2 A_CBE_L3 A_CBE_L4 A_CBE_L5 A_CBE_L6 A_CBE_L7 A_COMPAT A_DEVSEL# A_FRAME# A_GNT0# A_GNT1# A_GNT2# A_GNT3# A_GNT4# A_IRDY# A_M66EN A_PAR A_PAR64 A_PCIXCAP A_PCLK0 A_PCLK1 A_PCLK2 A_PCLK3 A_PCLK4 A_PERR# A_PIRQA# A_PIRQB# A_PIRQC# A_PIRQD# A_PLLCLKI A_PLLCLKO A_PME# A_PRESET# A_REQ0# A_REQ1# A_REQ2# A_REQ3# Ball AG14 AH14 AJ14 AE15 AG15 AJ15 AJ16 AH16 AG16 AF16 AE16 AD16 AJ17 AH20 AG22 AJ24 AJ26 AG17 AF17 AE17 AD17 K24 AG23 AD23 AC25 U25 R25 P25 N24 AE23 AE20 AF22 AH17 AH23 AB24 T24 R24 P24 N25 AD22 U24 V25 AA24 AB25 M25 M24 AD7 AC26 AC24 V24 T25 R26 Signal name A_REQ4# A_REQ64# A_SERR# A_STOP# A_TRDY# B_ACK64# B_AD0 B_AD1 B_AD2 B_AD3 B_AD4 B_AD5 B_AD6 B_AD7 B_AD8 B_AD9 B_AD10 B_AD11 B_AD12 B_AD13 B_AD14 B_AD15 B_AD16 B_AD17 B_AD18 B_AD19 B_AD20 B_AD21 B_AD22 B_AD23 B_AD24 B_AD25 B_AD26 B_AD27 B_AD28 B_AD29 B_AD30 B_AD31 B_AD32 B_AD33 B_AD34 B_AD35 B_AD36 B_AD37 B_AD38 B_AD39 B_AD40 B_AD41 B_AD42 B_AD43 B_AD44 B_AD45 Ball L26 AJ18 AE22 AJ23 AF23 P5 P4 P3 P2 P1 R1 R2 R3 R4 R6 T1 T5 U1 U2 U3 U4 U5 Y2 Y3 Y4 Y5 Y6 AA1 AA2 AA3 AA5 AA6 AB1 AB3 AB5 AC1 AC2 AC3 F4 F3 F2 F1 G5 G3 G1 H6 H5 H4 H3 H2 H1 J6 Signal name B_AD46 B_AD47 B_AD48 B_AD49 B_AD50 B_AD51 B_AD52 B_AD53 B_AD54 B_AD55 B_AD56 B_AD57 B_AD58 B_AD59 B_AD60 B_AD61 B_AD62 B_AD63 B_CBE_L0 B_CBE_L1 B_CBE_L2 B_CBE_L3 B_CBE_L4 B_CBE_L5 B_CBE_L6 B_CBE_L7 B_DEVSEL# B_FRAME# B_GNT0# B_GNT1# B_GNT2# B_GNT3# B_GNT4# B_IRDY# B_M66EN B_PAR B_PAR64 B_PCIXCAP B_PCLK0 B_PCLK1 B_PCLK2 B_PCLK3 B_PCLK4 B_PERR# B_PIRQA# B_PIRQB# B_PIRQC# B_PIRQD# B_PLLCLKI B_PLLCLKO B_PME# B_PRESET# Ball J5 J4 J3 J2 J1 K5 K3 K1 L6 L5 L4 L3 L2 L1 M6 M5 M4 M3 R5 U6 Y1 AA4 M1 N5 N3 N1 V6 W5 AC5 AF3 AG6 AG7 AG8 W3 T3 V1 M2 V5 AC6 AF4 AH6 AH7 AF9 V3 AE1 AD4 AD3 AD2 AE6 AE7 AD6 AD1
Table 18: Alphabetical listing of signals A_ACK64# to B_PRESET#.
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AMD-8131TM PCI-X Tunnel Data Sheet
Signal name B_REQ0# B_REQ1# B_REQ2# B_REQ3# B_REQ4# B_REQ64# B_SERR# B_STOP# B_TRDY# CMPOVR FREE1 FREE2 FREE3 FREE4 FREE5 FREE6 FREE7 FREE8 FREE9 FREE10 FREE12 FREE13 FREE14 FREE15 FREE16 FREE17 FREE18 FREE19 FREE20 FREE21 FREE22 HPSIC HPSIL# HPSOC HPSOD LDTCOMP0 LDTCOMP1 LDTCOMP2 LDTCOMP3 LDTSTOP# LRACAD_N0 LRACAD_N1 LRACAD_N2 LRACAD_N3 LRACAD_N4 LRACAD_N5 LRACAD_N6
Ball AC4 AF1 AF6 AF7 AE8 P6 V2 V4 W1 A27 D4 AJ5 AG9 AJ8 F5 AD5 AJ9 AD10 AJ3 D2 D1 E3 E4 AD9 AG1 AE5 E1 E2 AG2 AJ4 AE9 AJ6 J26 AJ7 J25 B4 A3 B2 C3 C27 B25 A24 B23 A22 A20 B19 A18
Signal name LRACAD_N12 LRACAD_N13 LRACAD_N14 LRACAD_N15 LRACAD_P0 LRACAD_P1 LRACAD_P2 LRACAD_P3 LRACAD_P4 LRACAD_P5 LRACAD_P6 LRACAD_P7 LRACAD_P8 LRACAD_P9 LRACAD_P10 LRACAD_P11 LRACAD_P12 LRACAD_P13 LRACAD_P14 LRACAD_P15 LRACLK0_N LRACLK0_P LRACLK1_N LRACLK1_P LRACTL_N LRACTL_P LRBCAD_N0 LRBCAD_N1 LRBCAD_N2 LRBCAD_N3 LRBCAD_N4 LRBCAD_N5 LRBCAD_N6 LRBCAD_N7 LRBCAD_P0 LRBCAD_P1 LRBCAD_P2 LRBCAD_P3 LRBCAD_P4 LRBCAD_P5 LRBCAD_P6 LRBCAD_P7 LRBCLK0_N LRBCLK0_P LRBCTL_N LRBCTL_P LTACAD_N0
Ball D20 E18 D18 E16 C25 A25 C23 A23 A21 C19 A19 C17 E25 C24 E23 C22 C20 E19 C18 E17 B21 C21 E20 E21 A16 A17 AD28 AC29 AB28 AA29 W29 V28 U29 T28 AD27 AD29 AB27 AB29 Y29 V27 V29 T27 Y28 Y27 R29 T29 A7
Signal name LTACAD_N6 LTACAD_N7 LTACAD_N8 LTACAD_N9 LTACAD_N1 0 LTACAD_N1 1 LTACAD_N1 2 LTACAD_N1 3 LTACAD_N1 4 LTACAD_N1 5 LTACAD_P0 LTACAD_P1 LTACAD_P2 LTACAD_P3 LTACAD_P4 LTACAD_P5 LTACAD_P6 LTACAD_P7 LTACAD_P8 LTACAD_P9 LTACAD_P10 LTACAD_P11 LTACAD_P12 LTACAD_P13 LTACAD_P14 LTACAD_P15 LTACLK0_N LTACLK0_P LTACLK1_N LTACLK1_P LTACTL_N0 LTACTL_P0 LTBCAD_N0 LTBCAD_N1 LTBCAD_N2 LTBCAD_N3 LTBCAD_N4 LTBCAD_N5 LTBCAD_N6 LTBCAD_N7 LTBCAD_P0 LTBCAD_P1 LTBCAD_P2 LTBCAD_P3 LTBCAD_P4 LTBCAD_P5 LTBCAD_P6
Ball C13 A15 C6 E7 C8 E9 E11 C12 E13 C14 A6 B7 A8 B9 B11 A12 B13 A14 D6 E6 D8 E8 E10 D12 E12 D14 A11 A10 C10 D10 C15 B15 F29 F27 H29 H27 K27 M29 M27 P29 E29 F28 G29 H28 K28 L29 M28
Signal name NC0 NC1 NC2 NC3 NIOAIRQA# NIOAIRQB# NIOAIRQC# NIOAIRQD# P_CAL P_CAL# PWROK REFCLK RESET# RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 STRAPL2 STRAPL3 TEST VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A
Ball AG4 AG5 AH3 AH4 F25 G24 G26 G25 AE3 AF2 C28 C29 B28 E14 E15 D16 C16 J27 K25 L24 L25 L27 N26 N27 R27 U26 U27 W24 W25 W26 W27 Y25 AA25 AA26 AA27 AC27 B27 H25 D27 H10 H18 J11 J17 K10 K18 L11 L17
Signal name VDD12B VDD12B VDD12B VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18
Ball V20 W19 W21 AA23 AC28 AD26 B12 B16 B20 B24 B8 D11 D15 D19 D23 D7 F10 F12 F14 F16 F18 F20 F22 F24 F8 G11 G13 G15 G17 G19 G21 G23 G28 G7 G9 H12 H14 H16 H20 H22 H26 H8 J13 J15 J19 J21 J23
Table 19: Alphabetical listing of signals B_REQ0# to VDD18. 79
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AMD-8131TM PCI-X Tunnel Data Sheet
LRACAD_N7 LRACAD_N8 LRACAD_N9 LRACAD_N10 LRACAD_N11
B17 E24 D24 E22 D22
LTACAD_N1 LTACAD_N2 LTACAD_N3 LTACAD_N4 LTACAD_N5
C7 A9 C9 C11 A13
LTBCAD_P7 LTBCLK0_N LTBCLK0_P LTBCTL_N LTBCTL_P
N29 K29 J29 P27 P28
VDD12B VDD12B VDD12B VDD12B VDD12B
L19 L21 M18 M20 V18
VDD18 VDD18 VDD18 VDD18 VDD18
K12 K14 K16 K20 K22
Table 19: Alphabetical listing of signals B_REQ0# to VDD18.
Signal name VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18
Ball L13 L15 L23 L28 M12 M14 M16 M22 M26 N13 N15 N17 N19 N21 N23 P12 P14 P16 P18 P20 P22 R13 R15 R17 R19 R21 R23 R28 T12 T14 T16 T18 T20 T22 T26 U13 U15 U17 U19 U21 U23 V12 V14 V16 V22
Signal name VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
Ball AA17 AA19 AA21 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB4 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC7 AC9 AD12 AD18 AD24 AE4 AF12 AF15 AF18 AF21 AF24 AF27 AF5 AF8 AG3 G4 J7 J9 K4 K6 K8 L7 L9
Signal name VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDDA18 VDDA18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball P8 R11 R7 R9 T10 T4 T6 T8 U11 U7 U9 V10 V8 W11 W13 W15 W17 W4 W7 W9 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y8 H24 AF29 AG29 A26 A4 A5 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA28 AA8 AB11 AB13
Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC8 AD15 AD21 AD8 AE10 AE2 AE26 AE27 AE28 AE29 AF10 AG10 AH10 AH12 AH15 AH18 AH2 AH21 AH24 AH27 AH5 AH8 AH9 B10 B14 B18 B22 B26 B3 B5 B6 C1 C2 C26 C4 C5
Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball D3 D5 D9 E26 E27 E28 E5 F11 F13 F15 F17 F19 F21 F23 F26 F6 F7 F9 G10 G12 G14 G16 G18 G2 G20 G22 G27 G6 G8 H11 H13 H15 H17 H19 H21 H23 H7 H9 J10 J12 J14 J16 J18 J20 J22
Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball K19 K2 K21 K23 K26 K7 K9 L10 L12 L14 L16 L18 L20 L22 L8 M11 M13 M15 M17 M19 M21 M23 M7 M9 N10 N12 N14 N16 N18 N2 N20 N22 N28 N6 N8 P11 P13 P15 P17 P19 P21 P23 P26 P7 P9
Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball R8 T11 T13 T15 T17 T19 T2 T21 T23 T7 T9 U10 U12 U14 U16 U18 U20 U22 U28 U8 V11 V13 V15 V17 V19 V21 V23 V26 V7 V9 W10 W12 W14 W16 W18 W2 W20 W22 W6 W8 Y11 Y13 Y15 Y17 Y19
Table 20: Alphabetical listing of signals VDD18 to VSS. 80
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AMD-8131TM PCI-X Tunnel Data Sheet
VDD18 VDD18 VDD18 VDD18 VDD33 VDD33 VDD33
W23 W28 Y24 Y26 AA11 AA13 AA15
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
M10 M8 N11 N4 N7 N9 P10
VSS VSS VSS VSS VSS VSS VSS
AB15 AB17 AB19 AB2 AB21 AB23 AB26
VSS VSS VSS VSS VSS VSS VSS
D13 D17 D21 D25 D26 D28 D29
VSS VSS VSS VSS VSS VSS VSS
J24 J28 J8 K11 K13 K15 K17
VSS VSS VSS VSS VSS VSS VSS
R10 R12 R14 R16 R18 R20 R22
VSS VSS VSS VSS
Y21 Y23 Y7 Y9
Table 20: Alphabetical listing of signals VDD18 to VSS.
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8
Package Specification
(
A1 CORNER
D
)
D1
D3
Ob (Nx Plcs)
E3
E2
E
E1
e
D2
BOTTOM VIEW TOP VIEW
LID A2 A AMD PACKAGE SYMBOL VARIATIONS
SEE NOTES
NOT TO SCALE
SIDE VIEW
A1
xOLF829
GENERAL NOTES 1. All dimensions are specified in millimeters (mm). 2. Dimensioning and tolerancing per ASME-Y14.5M-1994. 3. This corner which consists of a triangle on both sides of the package identifies ball A1 corner and can be used for handling and orientation purposes. 4. Symbol "M" determines ball matrix size and "N" is number of balls. 5. Dimension "b" is measured at maximum solder ball diameter on a plane parallel to datum C. 6. "x" in front of package variation denotes non-qualified package per AMD 01-002.3. 7. The following features are not shown on drawings: a) Marking on die, label on package b) Laser elements c) Die and passive fudicials
D/E D1/E1 D2/E2 D3/E3 A A1 A2 e Ob M N aaa bbb ccc
min. 37.3 32.30 22.80 3.35 0.5 1.0 0.6 29
max. 37.7 32.70 23.20 3.67 0.7 1.2 0.9
35.56 BSC.
1.27 BSC
829 0.2 0.25 0.125
Figure 14: Package mechanical drawing.
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AMD-8131TM PCI-X Tunnel Data Sheet
9
Test
The IC includes the following test modes. Mode TEST A_REQ2# Operational High impedance NAND tree 0 1 1 X 0 0
A_REQ1#
A_REQ0# Notes
X 0 0
X 0 1
Table 21: Test modes.
9.1 High Impedance Mode
In high-impedance mode, all the signals of the IC are placed into the high-impedance state.
9.2 NAND Tree Mode
There are several NAND trees in the IC. Some of the inputs are differential (e.g., LR[B, A] pins); for these, the _P and _N pairs of signals are converted into a single signal that is part of the NAND tree, as shown in Signal_3 in the following diagram.
VDD Signal_1 Signal_2 Signal_3_P Signal_3_N Signal_41 Output signal NAND Tree Mode
...
+ -
1
to output signal
0
...
Figure 15: NAND tree.
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AMD-8131TM PCI-X Tunnel Data Sheet
NAND tree 1: output signal is B_REQ[3]#. However, the gate connected to the last signal in this NAND tree (LDTCOMP[3]) is an AND gate rather than a NAND gate; so the expected output of this NAND tree is inverted compared to the other NAND trees.
1 2 3 4 5 6 7 8 9 LRBCLK0_[P,N] LRBCAD_[P,N][0] LRBCAD_[P,N][1] LRBCAD_[P,N][2] LRBCAD_[P,N][3] LRBCAD_[P,N][4] LRBCAD_[P,N][5] LRBCAD_[P,N][6] LRBCAD_[P,N][7] 11 LTBCLK0_P 12 LTBCLK0_N 13 LTBCAD_P[0] 14 LTBCAD_N[0] 15 LTBCAD_P[1] 16 LTBCAD_N[1] 17 LTBCAD_P[2] 18 LTBCAD_N[2] 19 LTBCAD_P[3] 20 LTBCAD_N[3] 21 LTBCAD_P[4] 22 LTBCAD_N[4] 23 LTBCAD_P[5] 24 LTBCAD_N[5] 25 LTBCAD_P[6] 26 LTBCAD_N[6] 27 LTBCAD_P[7] 28 LTBCAD_N[7] 29 LTBCTL_P 30 LTBCTL_N 31 LDTCOMP[2] 32 LDTCOMP[3]
10 LRBCTL_[P,N]
NAND tree 2: output signal is B_REQ[2]#.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LRACLK0_[P,N] LRACLK1_[P,N] LRACAD_[P,N][0] LRACAD_[P,N][8] LRACAD_[P,N][1] LRACAD_[P,N][9] LRACAD_[P,N][2] LRACAD_[P,N][10] LRACAD_[P,N][3] LRACAD_[P,N][11] LRACAD_[P,N][4] LRACAD_[P,N][12] LRACAD_[P,N][5] LRACAD_[P,N][13] LRACAD_[P,N][6] LRACAD_[P,N][14] LRACAD_[P,N][7] LRACAD_[P,N][15] LRACTL_[P,N] LTACLK0_P 21 LTACLK0_N 22 LTACLK1_P 23 LTACLK1_N 24 LTACAD_P[0] 25 LTACAD_N[0] 26 LTACAD_P[8] 27 LTACAD_N[8] 28 LTACAD_P[1] 29 LTACAD_N[1] 30 LTACAD_P[9] 31 LTACAD_N[9] 32 LTACAD_P[2] 33 LTACAD_N[2] 34 LTACAD_P[10] 35 LTACAD_N[10] 36 LTACAD_P[3] 37 LTACAD_N[3] 38 LTACAD_P[11] 39 LTACAD_N[11] 40 LTACAD_P[4] 41 LTACAD_N[4] 42 LTACAD_P[12] 43 LTACAD_N[12] 44 LTACAD_P[5] 45 LTACAD_N[5] 46 LTACAD_P[13] 47 LTACAD_N[13] 48 LTACAD_P[6] 49 LTACAD_N[6] 50 LTACAD_P[14] 51 LTACAD_N[14] 52 LTACAD_P[7] 53 LTACAD_N[7] 54 LTACAD_P[15] 55 LTACAD_N[15] 56 LTACTL_P 57 LTACTL_N
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AMD-8131TM PCI-X Tunnel Data Sheet
NAND tree 3: output signal is B_REQ[1]#. 22 B_AD[54] 43 B_AD[3] 1 B_AD[32] 2 3 4 5 6 7 8 9
B_AD[36] B_AD[33] B_AD[34] B_AD[39] B_AD[35] B_AD[37] B_AD[40] B_AD[41] 23 B_AD[55] 24 B_AD[53] 25 B_AD[56] 26 B_AD[57] 27 B_AD[58] 28 B_AD[60] 29 B_AD[59] 30 B_AD[61] 31 B_AD[62] 32 B_AD[63] 33 B_PAR64 34 B_CBE_L[4] 35 B_CBE_L[5] 36 B_CBE_L[6] 37 B_CBE_L[7] 38 B_REQ64# 39 B_ACK64# 40 B_AD[0] 41 B_AD[1] 42 B_AD[2] 44 B_AD[8] 45 B_CBE_L[0] 46 B_AD[7] 47 B_AD[6] 48 B_AD[5] 49 B_AD[4] 50 B_AD[9] 51 B_M66EN 52 B_AD[10] 53 B_AD[11] 54 B_AD[12] 55 B_AD[13] 56 B_AD[14] 57 B_AD[15] 58 B_CBE_L[1] 59 B_PAR 60 B_SERR# 61 B_PERR# 62 B_STOP# 63 B_TRDY#
64 B_DEVSEL# 65 B_IRDY# 66 B_CBE_L[2] 67 B_AD[16] 68 B_FRAME# 69 B_AD[17] 70 B_AD[21] 71 B_AD[18] 72 B_AD[22] 73 B_AD[19] 74 B_AD[23] 75 B_AD[20] 76 B_CBE_L[3] 77 B_AD[26] 78 B_AD[27] 79 B_AD[29] 80 B_AD[24] 81 B_AD[30] 82 B_PRESET# 83 B_AD[25] 84 B_AD[31]
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
B_PIRQD# B_PIRQA# B_AD[28] B_PIRQC# B_GNT[0]# B_PIRQB# B_PCLK[1] B_PCLK[0] B_GNT[1]# B_PLLCLKI B_GNT[2]# B_PCLK[2] HPSIC B_PLLCLKO B_REQ[4]#
10 B_AD[38] 11 B_AD[45] 12 B_AD[42] 13 B_AD[46] 14 B_AD[43] 15 B_AD[44] 16 B_AD[47] 17 B_AD[48] 18 B_AD[49] 19 B_AD[50] 20 B_AD[51] 21 B_AD[52]
100 B_GNT[3]# 101 B_PCLK[4] 102 B_GNT[4]# 103 B_PCLK[3] 104 HPSOC
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AMD-8131TM PCI-X Tunnel Data Sheet
NAND tree 4: output signal is A_REQ[3]#.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A_AD[32] A_AD[33] A_AD[34] A_AD[35] A_AD[36] A_AD[37] A_AD[38] A_AD[39] A_AD[40] A_AD[41] A_AD[42] A_AD[43] A_AD[44] A_AD[45] A_AD[46] A_AD[47] A_AD[48] A_AD[49] A_AD[50] A_AD[51] A_AD[52] 22 A_AD[53] 23 A_AD[54] 24 A_AD[55] 25 A_AD[56] 26 A_AD[62] 27 A_AD[61] 28 A_AD[60] 29 A_AD[59] 30 A_AD[58] 31 A_AD[57] 32 A_CBE_L[4] 33 A_CBE_L[5] 34 A_CBE_L[6] 35 A_CBE_L[7] 36 A_PAR64 37 A_AD[63] 38 A_AD[0] 39 A_ACK64# 40 A_REQ64# 41 A_AD[4] 42 A_AD[3] 43 A_AD[5] 44 A_AD[6] 45 A_AD[2] 46 A_AD[1] 47 A_CBE_L[0] 48 A_AD[8] 49 A_AD[9] 50 A_M66EN 51 A_AD[7] 52 A_AD[11] 53 A_AD[12] 54 A_AD[13] 55 A_AD[10] 56 A_AD[14] 57 A_AD[15] 58 A_CBE_L[1] 59 A_PAR 60 A_SERR# 61 A_STOP# 62 A_PERR# 63 A_DEVSEL# 64 A_TRDY# 65 A_FRAME# 66 A_IRDY# 67 A_CBE_L[2] 68 A_AD[18] 69 A_CBE_L[3] 70 A_AD[27] 71 A_AD[16] 72 A_AD[19] 73 A_AD[24] 74 A_AD[29] 75 A_AD[20] 76 A_AD[25] 77 A_AD[28] 78 A_AD[21] 79 A_AD[26] 80 A_AD[22] 81 A_AD[30] 82 A_AD[31] 83 A_AD[17] 84 A_AD[23] 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 A_GNT[0]# A_PRESET# A_PCLK[0] A_PIRQD# A_PIRQC# A_PIRQB# A_GNT[1]# A_PIRQA# A_PCLK[1] A_GNT[2]# A_PCLK[2] A_PCLK[3] A_GNT[3]# A_GNT[4]# A_PCLK[4]
100 A_PLLCLKI 101 A_REQ[4]# 102 A_PLLCLKO 103 A_COMPAT
NAND tree 5: output signal is B_REQ[0]#.
1 2 3 4 5 HPSOD HPSIL# STRAPL[3] NIOAIRQC# NIOAIRQD# 6 7 8 9 NIOAIRQB# REFCLK NIOAIRQA# PWROK 11 RESET# 12 STRAPL[2] 13 CMPOVR
10 LDTSTOP#
Notes: * [B, A]_PCIXCAP, A_REQ[2:0]#, TEST, LDTCOMP[1:0], P_CAL, P_CAL#, [B, A]_PME# are not included in the NAND trees. * While in NAND-tree mode, the link and PCI-X compensation is placed at a "mid-band" value. * Internal PLLs are disabled by placing them in bypass mode
10 Appendix
10.1 Revision History Revision 3.01 * Initial Release. Revision 3.02 * Removed Preliminary
86
24637 Rev 3.02 - August 10, 2004
AMD-8131TM PCI-X Tunnel Data Sheet
* Added Error Conditions and Handling.
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